forked from M-Labs/artiq
Sayma HMC830: update interface and register writes. (#1068)
* Break the HMC830 init into separate functions for general purpose (but, integer-N) init, setting dividers and checking lock * Use 1.6mA ICP (which the loop filter was optimized for) * Go through the data sheet carefully and set all registers to the correct value (e.g. ensure that all settings are correctly optimized for integer-N usage) * Change divider values (now using 100MHz PFD, which should give lower noise in theory)
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hartytp
GitHub
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@ -1,15 +1,3 @@
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/*
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* HMC830 config:
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* 100MHz input, 1.2GHz output
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* fvco = (refclk / r_divider) * n_divider
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* fout = fvco/2
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*
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* HMC7043 config:
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* dac clock: 600MHz (div=2)
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* fpga clock: 150MHz (div=8)
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* sysref clock: 9.375MHz (div=128)
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*/
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mod clock_mux {
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use board_misoc::csr;
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@ -30,27 +18,6 @@ mod clock_mux {
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mod hmc830 {
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use board_misoc::{csr, clock};
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const HMC830_WRITES: [(u8, u32); 18] = [
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(0x0, 0x20),
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(0x1, 0x2),
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(0x2, 0x2), // r_divider
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(0x5, 0x1628),
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(0x5, 0x60a0),
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(0x5, 0xe110),
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(0x5, 0x2818),
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(0x5, 0xf88),
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(0x5, 0x7fb0),
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(0x5, 0x0),
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(0x6, 0x303ca),
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(0x7, 0x14d),
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(0x8, 0xc1beff),
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(0x9, 0x153fff),
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(0xa, 0x2046),
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(0xb, 0x7c061),
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(0xf, 0x81),
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(0x3, 0x30), // n_divider
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];
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fn spi_setup() {
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unsafe {
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while csr::converter_spi::idle_read() == 0 {}
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@ -112,19 +79,65 @@ mod hmc830 {
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Ok(())
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}
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pub fn init() -> Result<(), &'static str> {
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pub fn init() {
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// Configure HMC830 for integer-N operation
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// See "PLLs with integrated VCO- RF Applications Product & Operating
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// Guide"
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spi_setup();
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info!("loading configuration...");
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for &(addr, data) in HMC830_WRITES.iter() {
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write(addr, data);
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}
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info!(" ...done");
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info!("loading HMC830 configuration...");
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write(0x0, 0x20); // software reset
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write(0x0, 0x00); // normal operation
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write(0x6, 0x307ca); // integer-N mode (NB data sheet table 5.8 not self-consistent)
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write(0x7, 0x4d); // digital lock detect, 1/2 cycle window (6.5ns window)
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write(0x9, 0x2850); // charge pump: 1.6mA, no offset
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write(0xa, 0x2045); // for wideband devices like the HMC830
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write(0xb, 0x7c061); // for HMC830
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// VCO subsystem registers
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// NB software reset does not seem to reset these registers, so always
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// program them all!
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write(0x5, 0xf88); // 1: defaults
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write(0x5, 0x6010); // 2: mute output until output divider set
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write(0x5, 0x2818); // 3: wideband PLL defaults
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write(0x5, 0x60a0); // 4: HMC830 magic value
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write(0x5, 0x1628); // 5: HMC830 magic value
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write(0x5, 0x7fb0); // 6: HMC830 magic value
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write(0x5, 0x0); // ready for VCO auto-cal
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info!(" ...done");
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}
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pub fn set_dividers(r_div: u32, n_div: u32, m_div: u32, out_div: u32) {
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// VCO frequency: f_vco = (f_ref/r_div)*(n_int + n_frac/2**24)
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// VCO frequency range [1.5GHz, 3GHz]
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// Output frequency: f_out = f_vco/out_div
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// Max PFD frequency: 125MHz for integer-N, 100MHz for fractional
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// (mode B)
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// Max reference frequency: 350MHz, however f_ref >= 200MHz requires
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// setting 0x08[21]=1
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//
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// :param r_div: reference divider [1, 16383]
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// :param n_div: VCO divider, integer part. Integer-N mode: [16, 2**19-1]
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// fractional mode: [20, 2**19-4]
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// :param m_div: VCO divider, fractional part [0, 2**24-1]
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// :param out_div: output divider [1, 62] (0 mutes output)
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info!("setting HMC830 dividers...");
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write(0x5, 0x6010 + (out_div << 7) + (((out_div <= 2) as u32) << 15));
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write(0x5, 0x0); // ready for VCO auto-cal
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write(0x2, r_div);
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write(0x4, m_div);
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write(0x3, n_div);
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info!(" ...done");
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}
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pub fn check_locked() -> Result<(), &'static str> {
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info!("waiting for HMC830 lock...");
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let t = clock::get_ms();
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info!("waiting for lock...");
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while read(0x12) & 0x02 == 0 {
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if clock::get_ms() > t + 2000 {
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error!(" lock timeout. Register dump:");
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error!("lock timeout. Register dump:");
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for addr in 0x00..0x14 {
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// These registers don't exist (in the data sheet at least)
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if addr == 0x0d || addr == 0x0e { continue; }
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@ -142,10 +155,11 @@ mod hmc830 {
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pub mod hmc7043 {
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use board_misoc::csr;
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const DAC_CLK_DIV: u32 = 2;
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const FPGA_CLK_DIV: u32 = 8;
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const SYSREF_DIV: u32 = 128;
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const HMC_SYSREF_DIV: u32 = SYSREF_DIV*8; // Must be <= 4MHz
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// All frequencies assume 1.2GHz HMC830 output
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const DAC_CLK_DIV: u32 = 2; // 600MHz
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const FPGA_CLK_DIV: u32 = 8; // 150MHz
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const SYSREF_DIV: u32 = 128; // 9.375MHz
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const HMC_SYSREF_DIV: u32 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz)
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// enabled, divider, analog phase shift, digital phase shift
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const OUTPUT_CONFIG: [(bool, u32, u8, u8); 14] = [
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@ -315,7 +329,9 @@ pub fn init() -> Result<(), &'static str> {
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/* do not use other SPI devices before HMC830 SPI mode selection */
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hmc830::select_spi_mode();
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hmc830::detect()?;
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hmc830::init()?;
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hmc830::init();
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hmc830::set_dividers(1, 24, 0, 2); // 100MHz ref, 1.2GHz out
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hmc830::check_locked()?;
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hmc7043::enable()?;
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hmc7043::detect()?;
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