diff --git a/artiq/devices/core_dds.py b/artiq/devices/core_dds.py
index cb95ad910..229ef992c 100644
--- a/artiq/devices/core_dds.py
+++ b/artiq/devices/core_dds.py
@@ -17,9 +17,9 @@ class DDS:
 	@kernel
 	def pulse(self, frequency, duration):
 		if self._previous_frequency != frequency:
-			self.core.syscall("rtio_sync", self.rtio_channel) # wait until output is off
-			self.core.syscall("dds_program", self.reg_channel, frequency)
+			syscall("rtio_sync", self.rtio_channel) # wait until output is off
+			syscall("dds_program", self.reg_channel, frequency)
 			self._previous_frequency = frequency
-		self.core.syscall("rtio_set", now()-self.latency, self.rtio_channel, 1)
+		syscall("rtio_set", now()-self.latency, self.rtio_channel, 1)
 		delay(duration)
-		self.core.syscall("rtio_set", now()-self.latency, self.rtio_channel, 0)
+		syscall("rtio_set", now()-self.latency, self.rtio_channel, 0)
diff --git a/artiq/language/experiment.py b/artiq/language/experiment.py
index af8dca05b..a33773c01 100644
--- a/artiq/language/experiment.py
+++ b/artiq/language/experiment.py
@@ -57,9 +57,19 @@ def set_time_manager(time_manager):
 	global _time_manager
 	_time_manager = time_manager
 
+class _DummySyscallManager:
+	def do(self, *args):
+		raise NotImplementedError("Attempted to interpret kernel without a syscall manager")
+
+_syscall_manager = _DummySyscallManager()
+
+def set_syscall_manager(syscall_manager):
+	global _syscall_manager
+	_syscall_manager = syscall_manager
+
 # global namespace for kernels
 
-kernel_globals = "sequential", "parallel", "delay", "now", "at"
+kernel_globals = "sequential", "parallel", "delay", "now", "at", "syscall"
 
 class _Sequential:
 	def __enter__(self):
@@ -85,3 +95,6 @@ def now():
 
 def at(time):
 	_time_manager.set_time(time)
+
+def syscall(*args):
+	return _syscall_manager.do(*args)