forked from M-Labs/artiq
ad9910 adding phase, freq in progress
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@ -10,6 +10,8 @@ import logging
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import socket
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import math
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from artiq.coredevice import spi2, urukul
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logger = logging.getLogger(__name__)
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@ -469,6 +471,18 @@ class DDSHandler:
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class AD9910Handler:
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_AD9910_REG_FTW = 0x07
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# shifted by << 24 so need to shift >> by 24 to confirm
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# also is a length 8 during the address
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# and 32 for the actual value
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# for the data transfer -> spi.SPI_END is ORed in with the flags
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_AD9910_REG_POW = 0x08
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# the spi flag is from urukul
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# SPI_CONFIG = (0 * spi.SPI_OFFLINE | 0 * spi.SPI_END |
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# 0 * spi.SPI_INPUT | 1 * spi.SPI_CS_POLARITY |
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# 0 * spi.SPI_CLK_POLARITY | 0 * spi.SPI_CLK_PHASE |
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# 0 * spi.SPI_LSB_FIRST | 0 * spi.SPI_HALF_DUPLEX)
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def __init__(self, manager, cpld):
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self.manager = manager
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self.dds_channels = dict()
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@ -476,8 +490,8 @@ class AD9910Handler:
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# needs to change depending on the structure of the urukul driver
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def add_dds_channel(self, name, dds_channel_nr):
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dds_channel = dict()
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frequency_precision = max(0, math.ceil(math.log10(2**32 / self.sysclk) + 6)) # fixme
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phase_precision = max(0, math.ceil(math.log10(2**16)))
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# frequency_precision = max(0, math.ceil(math.log10(2**32 / self.sysclk) + 6)) # fixme
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# phase_precision = max(0, math.ceil(math.log10(2**16)))
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with self.manager.scope("dds", name):
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dds_channel["vcd_frequency"] = \
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self.manager.get_channel(name + "/frequency", 64,
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@ -492,6 +506,7 @@ class AD9910Handler:
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dds_channel["pow"] = None
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self.dds_channels[dds_channel_nr] = dds_channel
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self.selected_channel = None
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self.ftw_or_pow = None
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def process_message(self, message):
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if isinstance(message, OutputMessage):
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@ -505,14 +520,21 @@ class AD9910Handler:
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self.length = data >> 8 & 0x1f
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self.flags = data & 0xff
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elif address == 0: # write
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# TODO determine the various conditions for a write
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# TODO determine if it is a config write (ie setting the address)
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# check the values set for config
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# ensure that config has SPI_END flag + there is a chip_select
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# only accept chip_sel with ftw word
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self.channels["write"].set_value("{:032b}".format(data))
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dds_channel = self.dds_channels[self.chip_sel]
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if self.flags == urukul.SPI_CONFIG:
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# setting the address
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if data == 0x07:
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dds_channel["ftw_or_pow"] = True
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elif self.flags == urukul.SPI_CONFIG | spi2.SPI_END:
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if dds_channel["ftw_or_pow"]:
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frequency = data / 2**32 # TODO: add the actual conversion from mu to freq
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dds_channel["vcd_frequency"].set_value_double(frequency)
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else:
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addr = data >> 24
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if addr == 0x08: # pow is being set
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pow = (data >> 8) & 0xffff
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phase_offset = pow / 2**16 # TODO: use the actual conversion
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dds_channel["vcd_phase"].set_value_double(phase_offset)
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else:
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raise ValueError("bad address", address)
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