forked from M-Labs/artiq
artiq_coreboot: block until hotswap image is actually received.
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parent
804e69b144
commit
795a3e24d8
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@ -60,6 +60,8 @@ class _D2HMsgType(Enum):
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WATCHDOG_EXPIRED = 14
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CLOCK_FAILURE = 15
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HOTSWAP_IMMINENT = 16
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class _LogLevel(Enum):
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OFF = 0
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@ -332,6 +334,8 @@ class CommKernel:
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self._write_header(_H2DMsgType.HOTSWAP)
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self._write_bytes(image)
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self._read_empty(_D2HMsgType.HOTSWAP_IMMINENT)
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def load(self, kernel_library):
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self._write_header(_H2DMsgType.LOAD_KERNEL)
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self._write_bytes(kernel_library)
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@ -140,6 +140,8 @@ pub enum Reply<'a> {
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WatchdogExpired,
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ClockFailure,
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HotswapImminent,
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}
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impl<'a> Reply<'a> {
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@ -219,6 +221,9 @@ impl<'a> Reply<'a> {
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Reply::ClockFailure => {
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writer.write_u8(15)?;
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},
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Reply::HotswapImminent => {
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writer.write_u8(16)?;
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}
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}
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Ok(())
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}
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@ -116,6 +116,7 @@ fn host_read(stream: &mut TcpStream) -> io::Result<host::Request> {
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let request = host::Request::read_from(stream)?;
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match &request {
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&host::Request::LoadKernel(_) => debug!("comm<-host LoadLibrary(...)"),
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&host::Request::Hotswap(_) => debug!("comm<-host Hotswap(...)"),
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_ => debug!("comm<-host {:?}", request)
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}
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Ok(request)
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@ -269,8 +270,12 @@ fn process_host_message(io: &Io,
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}
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// artiq_coreboot
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host::Request::Hotswap(binary) =>
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unsafe { board::hotswap::run(&binary) },
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host::Request::Hotswap(binary) => {
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host_write(stream, host::Reply::HotswapImminent)?;
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stream.close()?;
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warn!("hotswapping firmware");
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unsafe { board::hotswap::run(&binary) }
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}
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// artiq_run/artiq_master
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host::Request::SwitchClock(clk) => {
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