srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

sinara_tester/mirny: remove hw_rev checking fixup code 

Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
This commit is contained in:
Etienne Wodey 2021-01-29 18:47:40 +01:00
parent 6f8e788620
commit 78e1b9f8e5
1 changed files with 1 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
artiq/frontend/artiq_sinara_tester.py
View File

@ -291,18 +291,7 @@ class SinaraTester(EnvExperiment):
@kernel
def init_mirny(self, cpld):
self.core.break_realtime()
# Taken from Mirny.init(), to accomodate Mirny v1.1 without blinding
reg0 = cpld.read_reg(0)
if reg0 & 0b11 != 0b10: # Modified part
raise ValueError("Mirny HW_REV mismatch")
if (reg0 >> 2) & 0b11 != 0b00:
raise ValueError("Mirny PROTO_REV mismatch")
delay(100 * us) # slack
# select clock source
cpld.write_reg(1, (cpld.clk_sel << 4))
delay(1000 * us)
# End of modified Mirny.init()
cpld.init()
@kernel
def setup_mirny(self, channel, frequency):