diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
index 8f4793474..8191b187c 100755
--- a/artiq/gateware/targets/kc705.py
+++ b/artiq/gateware/targets/kc705.py
@@ -175,7 +175,7 @@ class NIST_QC1(_NIST_QCx):
 
         self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
         self.config["DDS_CHANNEL_COUNT"] = 8
-        self.add_constant("DDS_AD9858")
+        self.config["DDS_AD9858"] = 1
         phy = dds.AD9858(platform.request("dds"), 8)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy,
@@ -219,8 +219,8 @@ class NIST_QC2(_NIST_QCx):
 
         self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
         self.config["DDS_CHANNEL_COUNT"] = 11
-        self.add_constant("DDS_AD9914")
-        self.add_constant("DDS_ONEHOT_SEL")
+        self.config["DDS_AD9914"] = True
+        self.config["DDS_ONEHOT_SEL"] = True
         phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy,
diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py
index 95e493bbc..6a561f9b7 100755
--- a/artiq/gateware/targets/pipistrello.py
+++ b/artiq/gateware/targets/pipistrello.py
@@ -181,7 +181,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
 
         self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
         self.config["DDS_CHANNEL_COUNT"] = 8
-        self.add_constant("DDS_AD9858")
+        self.config["DDS_AD9858"] = True
         dds_pins = platform.request("dds")
         self.comb += dds_pins.p.eq(0)
         phy = dds.AD9858(dds_pins, 8)
diff --git a/artiq/runtime/bridge.c b/artiq/runtime/bridge.c
index 54286b7ae..708e35473 100644
--- a/artiq/runtime/bridge.c
+++ b/artiq/runtime/bridge.c
@@ -20,10 +20,10 @@ static int dds_read(int addr)
 {
     int r;
 
-#ifdef DDS_AD9858
+#ifdef CONFIG_DDS_AD9858
 #define DDS_READ_FLAG 128
 #endif
-#ifdef DDS_AD9914
+#ifdef CONFIG_DDS_AD9914
 #define DDS_READ_FLAG 256
 #endif
     dds_write(addr | DDS_READ_FLAG, 0);
diff --git a/artiq/runtime/dds.c b/artiq/runtime/dds.c
index 543cec4cb..93ade0569 100644
--- a/artiq/runtime/dds.c
+++ b/artiq/runtime/dds.c
@@ -8,12 +8,12 @@
 
 #define DURATION_WRITE (5 << CONFIG_RTIO_FINE_TS_WIDTH)
 
-#if defined DDS_AD9858
+#if defined CONFIG_DDS_AD9858
 /* Assume 8-bit bus */
 #define DURATION_INIT (7*DURATION_WRITE) /* not counting FUD */
 #define DURATION_PROGRAM (8*DURATION_WRITE) /* not counting FUD */
 
-#elif defined DDS_AD9914
+#elif defined CONFIG_DDS_AD9914
 /* Assume 16-bit bus */
 /* DAC calibration takes max. 1ms as per datasheet */
 #define DURATION_DAC_CAL (147000 << CONFIG_RTIO_FINE_TS_WIDTH)
@@ -46,7 +46,7 @@ void dds_init(long long int timestamp, int channel)
 #endif
     channel <<= 1;
     DDS_WRITE(DDS_GPIO, channel);
-#ifndef DDS_AD9914
+#ifndef CONFIG_DDS_AD9914
     /*
      * Resetting a AD9914 intermittently crashes it. It does not produce any
      * output until power-cycled.
@@ -58,7 +58,7 @@ void dds_init(long long int timestamp, int channel)
     DDS_WRITE(DDS_GPIO, channel);
 #endif
 
-#ifdef DDS_AD9858
+#ifdef CONFIG_DDS_AD9858
     /*
      * 2GHz divider disable
      * SYNCLK disable
@@ -72,7 +72,7 @@ void dds_init(long long int timestamp, int channel)
     DDS_WRITE(DDS_FUD, 0);
 #endif
 
-#ifdef DDS_AD9914
+#ifdef CONFIG_DDS_AD9914
     DDS_WRITE(DDS_CFR1H, 0x0000); /* Enable cosine output */
     DDS_WRITE(DDS_CFR2L, 0x8900); /* Enable matched latency */
     DDS_WRITE(DDS_CFR2H, 0x0080); /* Enable profile mode */
@@ -105,14 +105,14 @@ static void dds_set_one(long long int now, long long int ref_time, unsigned int
 #endif
     DDS_WRITE(DDS_GPIO, channel_enc << 1);
 
-#ifdef DDS_AD9858
+#ifdef CONFIG_DDS_AD9858
     DDS_WRITE(DDS_FTW0, ftw & 0xff);
     DDS_WRITE(DDS_FTW1, (ftw >> 8) & 0xff);
     DDS_WRITE(DDS_FTW2, (ftw >> 16) & 0xff);
     DDS_WRITE(DDS_FTW3, (ftw >> 24) & 0xff);
 #endif
 
-#ifdef DDS_AD9914
+#ifdef CONFIG_DDS_AD9914
     DDS_WRITE(DDS_FTWL, ftw & 0xffff);
     DDS_WRITE(DDS_FTWH, (ftw >> 16) & 0xffff);
 #endif
@@ -122,10 +122,10 @@ static void dds_set_one(long long int now, long long int ref_time, unsigned int
      */
     if(phase_mode == PHASE_MODE_CONTINUOUS) {
         /* Do not clear phase accumulator on FUD */
-#ifdef DDS_AD9858
+#ifdef CONFIG_DDS_AD9858
         DDS_WRITE(DDS_CFR2, 0x00);
 #endif
-#ifdef DDS_AD9914
+#ifdef CONFIG_DDS_AD9914
         /* Disable autoclear phase accumulator and enables OSK. */
         DDS_WRITE(DDS_CFR1L, 0x0108);
 #endif
@@ -134,10 +134,10 @@ static void dds_set_one(long long int now, long long int ref_time, unsigned int
         long long int fud_time;
 
         /* Clear phase accumulator on FUD */
-#ifdef DDS_AD9858
+#ifdef CONFIG_DDS_AD9858
         DDS_WRITE(DDS_CFR2, 0x40);
 #endif
-#ifdef DDS_AD9914
+#ifdef CONFIG_DDS_AD9914
         /* Enable autoclear phase accumulator and enables OSK. */
         DDS_WRITE(DDS_CFR1L, 0x2108);
 #endif
@@ -148,14 +148,14 @@ static void dds_set_one(long long int now, long long int ref_time, unsigned int
         continuous_phase_comp[channel] = pow;
     }
 
-#ifdef DDS_AD9858
+#ifdef CONFIG_DDS_AD9858
     DDS_WRITE(DDS_POW0, pow & 0xff);
     DDS_WRITE(DDS_POW1, (pow >> 8) & 0x3f);
 #endif
-#ifdef DDS_AD9914
+#ifdef CONFIG_DDS_AD9914
     DDS_WRITE(DDS_POW, pow);
 #endif
-#ifdef DDS_AD9914
+#ifdef CONFIG_DDS_AD9914
     DDS_WRITE(DDS_ASF, amplitude);
 #endif
     DDS_WRITE(DDS_FUD, 0);
diff --git a/artiq/runtime/dds.h b/artiq/runtime/dds.h
index 2c2247b04..6d4e5d972 100644
--- a/artiq/runtime/dds.h
+++ b/artiq/runtime/dds.h
@@ -8,7 +8,7 @@
 /* Maximum number of commands in a batch */
 #define DDS_MAX_BATCH 16
 
-#ifdef DDS_AD9858
+#ifdef CONFIG_DDS_AD9858
 #define DDS_CFR0  0x00
 #define DDS_CFR1  0x01
 #define DDS_CFR2  0x02
@@ -23,7 +23,7 @@
 #define DDS_GPIO  0x41
 #endif
 
-#ifdef DDS_AD9914
+#ifdef CONFIG_DDS_AD9914
 #define DDS_CFR1L  0x01
 #define DDS_CFR1H  0x03
 #define DDS_CFR2L  0x05
@@ -40,11 +40,11 @@
 #define DDS_GPIO   0x81
 #endif
 
-#ifdef DDS_AD9858
+#ifdef CONFIG_DDS_AD9858
 #define DDS_POW_WIDTH 14
 #endif
 
-#ifdef DDS_AD9914
+#ifdef CONFIG_DDS_AD9914
 #define DDS_POW_WIDTH 16
 #endif
 
diff --git a/artiq/runtime/test_mode.c b/artiq/runtime/test_mode.c
index f0254aea0..8c7f47c0c 100644
--- a/artiq/runtime/test_mode.c
+++ b/artiq/runtime/test_mode.c
@@ -166,10 +166,10 @@ static void ddsr(char *addr)
         return;
     }
 
-#ifdef DDS_AD9858
+#ifdef CONFIG_DDS_AD9858
     printf("0x%02x\n", brg_ddsread(addr2));
 #endif
-#ifdef DDS_AD9914
+#ifdef CONFIG_DDS_AD9914
     printf("0x%04x\n", brg_ddsread(addr2));
 #endif
 }
@@ -205,13 +205,13 @@ static void ddsftw(char *n, char *ftw)
 #endif
     brg_ddssel(n2);
 
-#ifdef DDS_AD9858
+#ifdef CONFIG_DDS_AD9858
     brg_ddswrite(DDS_FTW0, ftw2 & 0xff);
     brg_ddswrite(DDS_FTW1, (ftw2 >> 8) & 0xff);
     brg_ddswrite(DDS_FTW2, (ftw2 >> 16) & 0xff);
     brg_ddswrite(DDS_FTW3, (ftw2 >> 24) & 0xff);
 #endif
-#ifdef DDS_AD9914
+#ifdef CONFIG_DDS_AD9914
     brg_ddswrite(DDS_FTWL, ftw2 & 0xffff);
     brg_ddswrite(DDS_FTWH, (ftw2 >> 16) & 0xffff);
 #endif
@@ -224,7 +224,7 @@ static void ddsreset(void)
     brg_ddsreset();
 }
 
-#ifdef DDS_AD9858
+#ifdef CONFIG_DDS_AD9858
 static void ddsinit(void)
 {
     brg_ddsreset();
@@ -236,7 +236,7 @@ static void ddsinit(void)
 }
 #endif
 
-#ifdef DDS_AD9914
+#ifdef CONFIG_DDS_AD9914
 static void ddsinit(void)
 {
     long long int t;
@@ -273,24 +273,24 @@ static void do_ddstest_one(unsigned int i)
 
     for(j=0; j<12; j++) {
         f = v[j];
-#ifdef DDS_AD9858
+#ifdef CONFIG_DDS_AD9858
         brg_ddswrite(DDS_FTW0, f & 0xff);
         brg_ddswrite(DDS_FTW1, (f >> 8) & 0xff);
         brg_ddswrite(DDS_FTW2, (f >> 16) & 0xff);
         brg_ddswrite(DDS_FTW3, (f >> 24) & 0xff);
 #endif
-#ifdef DDS_AD9914
+#ifdef CONFIG_DDS_AD9914
         brg_ddswrite(DDS_FTWL, f & 0xffff);
         brg_ddswrite(DDS_FTWH, (f >> 16) & 0xffff);
 #endif
         brg_ddsfud();
-#ifdef DDS_AD9858
+#ifdef CONFIG_DDS_AD9858
         g = brg_ddsread(DDS_FTW0);
         g |= brg_ddsread(DDS_FTW1) << 8;
         g |= brg_ddsread(DDS_FTW2) << 16;
         g |= brg_ddsread(DDS_FTW3) << 24;
 #endif
-#ifdef DDS_AD9914
+#ifdef CONFIG_DDS_AD9914
         g = brg_ddsread(DDS_FTWL);
         g |= brg_ddsread(DDS_FTWH) << 16;
 #endif