forked from M-Labs/artiq
kc705: port amc101_dac/spi0 and sma_spi to spi2
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21b1757bfd
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@ -119,7 +119,7 @@ device_db = {
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# Generic SPI
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"spi0": {
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"type": "local",
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"module": "artiq.coredevice.spi",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 23}
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},
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@ -161,7 +161,7 @@ device_db = {
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# DAC
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"spi_ams101": {
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"type": "local",
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"module": "artiq.coredevice.spi",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 22}
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},
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@ -319,7 +319,7 @@ class NIST_CLOCK(_StandaloneBase):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = spi.SPIMaster(ams101_dac)
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phy = spi2.SPIMaster(ams101_dac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=4))
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@ -423,7 +423,7 @@ class NIST_QC2(_StandaloneBase):
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# add clock generators after TTLs
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rtio_channels += clock_generators
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phy = spi.SPIMaster(ams101_dac)
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phy = spi2.SPIMaster(ams101_dac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=4))
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@ -478,12 +478,12 @@ class SMA_SPI(_StandaloneBase):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = spi.SPIMaster(ams101_dac)
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phy = spi2.SPIMaster(ams101_dac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=4))
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phy = spi.SPIMaster(self.platform.request("sma_spi"))
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phy = spi2.SPIMaster(self.platform.request("sma_spi"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=128))
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