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novogorny: conv -> cnv 

* parity with sampler
* also add novogorny device to opticlock
This commit is contained in:
Robert Jördens 2018-03-21 18:38:39 +00:00
parent 82c4f0eed4
commit 770b0a7b79
3 changed files with 18 additions and 9 deletions
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12
artiq/coredevice/novogorny.py
View File

@ -67,17 +67,17 @@ class Novogorny:
register.
:param spi_device: SPI bus device name
:param conv_device: CONV RTIO TTLOut channel name
:param cnv_device: CNV RTIO TTLOut channel name
:param div: SPI clock divider (default: 8)
:param core_device: Core device name
"""
kernel_invariants = {"bus", "core", "conv", "div", "v_ref"}
kernel_invariants = {"bus", "core", "cnv", "div", "v_ref"}
def __init__(self, dmgr, spi_device, conv_device, div=8,
def __init__(self, dmgr, spi_device, cnv_device, div=8,
core_device="core"):
self.bus = dmgr.get(spi_device)
self.core = dmgr.get(core_device)
self.conv = dmgr.get(conv_device)
self.cnv = dmgr.get(cnv_device)
self.div = div
self.gains = 0x0000
self.v_ref = 5. # 5 Volt reference
@ -125,7 +125,7 @@ class Novogorny:
:param next_ctrl: ADC control word for the next sample
:return: The ADC result packet (machine units)
"""
self.conv.pulse(40*ns) # t_CNVH
self.cnv.pulse(40*ns) # t_CNVH
delay(560*ns) # t_CONV max
self.bus.set_config_mu(SPI_CONFIG | spi.SPI_INPUT | spi.SPI_END,
24, self.div, SPI_CS_ADC)
@ -163,7 +163,7 @@ class Novogorny:
24, self.div, SPI_CS_ADC)
for i in range(len(data)):
t0 = now_mu()
self.conv.pulse(40*ns) # t_CNVH
self.cnv.pulse(40*ns) # t_CNVH
delay(560*ns) # t_CONV max
self.bus.write(ctrl << 24)
at_mu(t0 + dt_mu)

11
artiq/examples/kasli_opticlock/device_db.py
View File

@ -192,12 +192,21 @@ device_db = {
"class": "SPIMaster",
"arguments": {"channel": 24}
},
"ttl_novogorny0_conv": {
"ttl_novogorny0_cnv": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 25}
},
"novogorny0" : {
"type": "local",
"module": "artiq.coredevice.novogorny",
"class": "Novogorny",
"arguments": {
"spi_device": "spi_novogorny0",
"cnv_device": "ttl_novogorny0_cnv",
}
},
"spi_urukul0": {
"type": "local",

4
artiq/gateware/targets/kasli.py
View File

@ -247,7 +247,7 @@ def _novogorny(eem):
Subsignal("n", Pins(_eem_pin(j, i, "n"))),
IOStandard("LVDS_25")
) for i, j, sig in [
(5, eem, "conv"),
(5, eem, "cnv"),
(6, eem, "busy"),
(7, eem, "scko"),
]
@ -369,7 +369,7 @@ class Opticlock(_StandaloneBase):
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=16))
for signal in "conv".split():
for signal in "cnv".split():
pads = platform.request("eem3_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy