firmware: split libdrtioaux into libproto and libboard_artiq modules.

All other protocol code lives in libproto, and all other gateware
interfaces live in libboard_artiq.

artiq/firmware/Cargo.lock

@@ -35,7 +35,10 @@ dependencies = [
  "build_artiq 0.0.0",
  "build_misoc 0.0.0",
  "byteorder 1.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
+ "crc 1.7.0 (registry+https://github.com/rust-lang/crates.io-index)",
+ "io 0.0.0",
  "log 0.4.1 (registry+https://github.com/rust-lang/crates.io-index)",
+ "proto 0.0.0",
 ]
 
 [[package]]
@@ -98,17 +101,6 @@ name = "cslice"
 version = "0.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 
-[[package]]
-name = "drtioaux"
-version = "0.0.0"
-dependencies = [
- "board 0.0.0",
- "build_misoc 0.0.0",
- "crc 1.7.0 (registry+https://github.com/rust-lang/crates.io-index)",
- "io 0.0.0",
- "log 0.4.1 (registry+https://github.com/rust-lang/crates.io-index)",
-]
-
 [[package]]
 name = "dyld"
 version = "0.0.0"
@@ -219,7 +211,6 @@ dependencies = [
  "build_misoc 0.0.0",
  "byteorder 1.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
  "cslice 0.3.0 (registry+https://github.com/rust-lang/crates.io-index)",
- "drtioaux 0.0.0",
  "fringe 1.1.0 (git+https://github.com/m-labs/libfringe?rev=bd23494)",
  "io 0.0.0",
  "log 0.4.1 (registry+https://github.com/rust-lang/crates.io-index)",
@@ -248,7 +239,6 @@ dependencies = [
  "board_artiq 0.0.0",
  "build_artiq 0.0.0",
  "build_misoc 0.0.0",
- "drtioaux 0.0.0",
  "log 0.4.1 (registry+https://github.com/rust-lang/crates.io-index)",
 ]
 

artiq/firmware/libboard_artiq/Cargo.toml

@@ -15,7 +15,10 @@ build_artiq = { path = "../libbuild_artiq" }
 [dependencies]
 bitflags = "1.0"
 byteorder = { version = "1.0", default-features = false }
+crc = { version = "1.7", default-features = false }
 log = { version = "0.4", default-features = false }
+io = { path = "../libio", features = ["byteorder"] }
+proto = { path = "../libproto" }
 board = { path = "../libboard" }
 
 [features]

artiq/firmware/libboard_artiq/drtioaux.rs

@@ -1,8 +1,11 @@
-use core::fmt;
+use core::{slice, fmt, result};
-use io::{Cursor, Error as IoError};
+use crc;
-use io::proto::ProtoRead;
 
-use super::*;
+use io::{Cursor, Error as IoError};
+use io::proto::{ProtoRead, ProtoWrite};
+use board;
+
+pub use proto::drtioaux_proto::Packet;
 
 pub type Result<T> = result::Result<T, Error>;
 

artiq/firmware/libboard_artiq/lib.rs

@@ -1,12 +1,15 @@
-#![feature(asm, lang_items)]
+#![feature(asm, lang_items, never_type)]
 #![no_std]
 
 #[macro_use]
 extern crate bitflags;
 extern crate byteorder;
+extern crate crc;
 #[macro_use]
 extern crate log;
 extern crate board;
+extern crate io;
+extern crate proto;
 
 pub mod pcr;
 
@@ -28,3 +31,6 @@ mod ad9154_reg;
 pub mod ad9154;
 #[cfg(has_allaki_atts)]
 pub mod hmc542;
+
+#[cfg(has_drtio)]
+pub mod drtioaux;

artiq/firmware/libdrtioaux/Cargo.toml

@@ -1,18 +0,0 @@
-[package]
-authors = ["M-Labs"]
-name = "drtioaux"
-version = "0.0.0"
-build = "build.rs"
-
-[lib]
-name = "drtioaux"
-path = "lib.rs"
-
-[build-dependencies]
-build_misoc = { path = "../libbuild_misoc" }
-
-[dependencies]
-log = { version = "0.4", default-features = false }
-crc = { version = "1.7", default-features = false }
-io = { path = "../libio", features = ["byteorder"] }
-board = { path = "../libboard" }

artiq/firmware/libdrtioaux/build.rs

@@ -1,5 +0,0 @@
-extern crate build_misoc;
-
-fn main() {
-    build_misoc::cfg();
-}

artiq/firmware/libproto/drtioaux_proto.rs

@@ -1,11 +1,3 @@
-#![no_std]
-#![feature(never_type)]
-
-extern crate crc;
-
-extern crate io;
-extern crate board;
-
 use io::{Read, Write, Error, Result};
 use io::proto::{ProtoRead, ProtoWrite};
 
@@ -264,6 +256,3 @@ impl Packet {
         Ok(())
     }
 }
-
-#[cfg(has_drtio)]
-pub mod hw;

artiq/firmware/libproto/lib.rs

@@ -13,6 +13,7 @@ extern crate dyld;
 
 // Internal protocols.
 pub mod kernel_proto;
+pub mod drtioaux_proto;
 
 // External protocols.
 #[cfg(feature = "alloc")]

artiq/firmware/runtime/Cargo.toml

@@ -27,7 +27,6 @@ logger_artiq = { path = "../liblogger_artiq" }
 board_artiq = { path = "../libboard_artiq" }
 proto = { path = "../libproto", features = ["log", "alloc"] }
 amp = { path = "../libamp" }
-drtioaux = { path = "../libdrtioaux" }
 
 [dependencies.fringe]
 git = "https://github.com/m-labs/libfringe"

artiq/firmware/runtime/kern_hwreq.rs

@@ -10,7 +10,7 @@ mod drtio_i2c {
     use drtioaux;
 
     fn basic_reply(nodeno: u8) -> Result<(), ()> {
-        match drtioaux::hw::recv_timeout(nodeno, None) {
+        match drtioaux::recv_timeout(nodeno, None) {
             Ok(drtioaux::Packet::I2cBasicReply { succeeded }) => {
                 if succeeded { Ok(()) } else { Err(()) }
             }
@@ -27,7 +27,7 @@ mod drtio_i2c {
 
     pub fn start(nodeno: u8, busno: u8) -> Result<(), ()> {
         let request = drtioaux::Packet::I2cStartRequest { busno: busno };
-        if drtioaux::hw::send(nodeno, &request).is_err() {
+        if drtioaux::send(nodeno, &request).is_err() {
             return Err(())
         }
         basic_reply(nodeno)
@@ -35,7 +35,7 @@ mod drtio_i2c {
 
     pub fn restart(nodeno: u8, busno: u8) -> Result<(), ()> {
         let request = drtioaux::Packet::I2cRestartRequest { busno: busno };
-        if drtioaux::hw::send(nodeno, &request).is_err() {
+        if drtioaux::send(nodeno, &request).is_err() {
             return Err(())
         }
         basic_reply(nodeno)
@@ -43,7 +43,7 @@ mod drtio_i2c {
 
     pub fn stop(nodeno: u8, busno: u8) -> Result<(), ()> {
         let request = drtioaux::Packet::I2cStopRequest { busno: busno };
-        if drtioaux::hw::send(nodeno, &request).is_err() {
+        if drtioaux::send(nodeno, &request).is_err() {
             return Err(())
         }
         basic_reply(nodeno)
@@ -54,10 +54,10 @@ mod drtio_i2c {
             busno: busno,
             data: data
         };
-        if drtioaux::hw::send(nodeno, &request).is_err() {
+        if drtioaux::send(nodeno, &request).is_err() {
             return Err(())
         }
-        match drtioaux::hw::recv_timeout(nodeno, None) {
+        match drtioaux::recv_timeout(nodeno, None) {
             Ok(drtioaux::Packet::I2cWriteReply { succeeded, ack }) => {
                 if succeeded { Ok(ack) } else { Err(()) }
             }
@@ -77,10 +77,10 @@ mod drtio_i2c {
             busno: busno,
             ack: ack
         };
-        if drtioaux::hw::send(nodeno, &request).is_err() {
+        if drtioaux::send(nodeno, &request).is_err() {
             return Err(())
         }
-        match drtioaux::hw::recv_timeout(nodeno, None) {
+        match drtioaux::recv_timeout(nodeno, None) {
             Ok(drtioaux::Packet::I2cReadReply { succeeded, data }) => {
                 if succeeded { Ok(data) } else { Err(()) }
             }
@@ -179,7 +179,7 @@ mod drtio_spi {
     use drtioaux;
 
     fn basic_reply(nodeno: u8) -> Result<(), ()> {
-        match drtioaux::hw::recv_timeout(nodeno, None) {
+        match drtioaux::recv_timeout(nodeno, None) {
             Ok(drtioaux::Packet::SpiBasicReply { succeeded }) => {
                 if succeeded { Ok(()) } else { Err(()) }
             }
@@ -202,7 +202,7 @@ mod drtio_spi {
             div: div,
             cs: cs
         };
-        if drtioaux::hw::send(nodeno, &request).is_err() {
+        if drtioaux::send(nodeno, &request).is_err() {
             return Err(())
         }
         basic_reply(nodeno)
@@ -213,7 +213,7 @@ mod drtio_spi {
             busno: busno,
             data: data
         };
-        if drtioaux::hw::send(nodeno, &request).is_err() {
+        if drtioaux::send(nodeno, &request).is_err() {
             return Err(())
         }
         basic_reply(nodeno)
@@ -221,10 +221,10 @@ mod drtio_spi {
 
     pub fn read(nodeno: u8, busno: u8) -> Result<u32, ()> {
         let request = drtioaux::Packet::SpiReadRequest { busno: busno };
-        if drtioaux::hw::send(nodeno, &request).is_err() {
+        if drtioaux::send(nodeno, &request).is_err() {
             return Err(())
         }
-        match drtioaux::hw::recv_timeout(nodeno, None) {
+        match drtioaux::recv_timeout(nodeno, None) {
             Ok(drtioaux::Packet::SpiReadReply { succeeded, data }) => {
                 if succeeded { Ok(data) } else { Err(()) }
             }

artiq/firmware/runtime/main.rs

@@ -21,8 +21,6 @@ extern crate board;
 extern crate board_artiq;
 extern crate proto;
 extern crate amp;
-#[cfg(has_drtio)]
-extern crate drtioaux;
 
 use core::convert::TryFrom;
 use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
@@ -31,7 +29,11 @@ use board::irq;
 use board::config;
 #[cfg(has_ethmac)]
 use board::ethmac;
-use proto::{mgmt_proto, analyzer_proto, moninj_proto, rpc_proto, session_proto, kernel_proto};
+#[cfg(has_drtio)]
+use board_artiq::drtioaux;
+use proto::{mgmt_proto, moninj_proto, rpc_proto, session_proto,kernel_proto};
+#[cfg(has_rtio_analyzer)]
+use proto::analyzer_proto;
 use amp::{mailbox, rpc_queue};
 
 #[cfg(has_rtio_core)]

artiq/firmware/runtime/moninj.rs

@@ -35,14 +35,14 @@ fn read_probe_local(channel: u16, probe: u8) -> u32 {
 #[cfg(has_drtio)]
 fn read_probe_drtio(nodeno: u8, channel: u16, probe: u8) -> u32 {
     let request = drtioaux::Packet::MonitorRequest { channel: channel, probe: probe };
-    match drtioaux::hw::send(nodeno, &request) {
+    match drtioaux::send(nodeno, &request) {
         Ok(_) => (),
         Err(e) => {
             error!("aux packet error ({})", e);
             return 0;
         }
     }
-    match drtioaux::hw::recv_timeout(nodeno, None) {
+    match drtioaux::recv_timeout(nodeno, None) {
         Ok(drtioaux::Packet::MonitorReply { value }) => return value,
         Ok(_) => error!("received unexpected aux packet"),
         Err(e) => error!("aux packet error ({})", e)
@@ -85,7 +85,7 @@ fn inject_drtio(nodeno: u8, channel: u16, overrd: u8, value: u8) {
         overrd: overrd,
         value: value
     };
-    match drtioaux::hw::send(nodeno, &request) {
+    match drtioaux::send(nodeno, &request) {
         Ok(_) => (),
         Err(e) => error!("aux packet error ({})", e)
     }
@@ -126,14 +126,14 @@ fn read_injection_status_drtio(nodeno: u8, channel: u16, overrd: u8) -> u8 {
         channel: channel,
         overrd: overrd
     };
-    match drtioaux::hw::send(nodeno, &request) {
+    match drtioaux::send(nodeno, &request) {
         Ok(_) => (),
         Err(e) => {
             error!("aux packet error ({})", e);
             return 0;
         }
     }
-    match drtioaux::hw::recv_timeout(nodeno, None) {
+    match drtioaux::recv_timeout(nodeno, None) {
         Ok(drtioaux::Packet::InjectionStatusReply { value }) => return value,
         Ok(_) => error!("received unexpected aux packet"),
         Err(e) => error!("aux packet error ({})", e)

artiq/firmware/runtime/rtio_mgt.rs

@@ -99,9 +99,9 @@ pub mod drtio {
                 return 0
             }
             count += 1;
-            drtioaux::hw::send_link(linkno, &drtioaux::Packet::EchoRequest).unwrap();
+            drtioaux::send_link(linkno, &drtioaux::Packet::EchoRequest).unwrap();
             io.sleep(100).unwrap();
-            let pr = drtioaux::hw::recv_link(linkno);
+            let pr = drtioaux::recv_link(linkno);
             match pr {
                 Ok(Some(drtioaux::Packet::EchoReply)) => return count,
                 _ => {}
@@ -131,8 +131,8 @@ pub mod drtio {
     }
 
     fn process_aux_errors(linkno: u8) {
-        drtioaux::hw::send_link(linkno, &drtioaux::Packet::RtioErrorRequest).unwrap();
+        drtioaux::send_link(linkno, &drtioaux::Packet::RtioErrorRequest).unwrap();
-        match drtioaux::hw::recv_timeout_link(linkno, None) {
+        match drtioaux::recv_timeout_link(linkno, None) {
             Ok(drtioaux::Packet::RtioNoErrorReply) => (),
             Ok(drtioaux::Packet::RtioErrorSequenceErrorReply { channel }) =>
                 error!("[LINK#{}] RTIO sequence error involving channel {}", linkno, channel),
@@ -183,9 +183,9 @@ pub mod drtio {
         for linkno in 0..csr::DRTIO.len() {
             let linkno = linkno as u8;
             if link_up(linkno) {
-                drtioaux::hw::send_link(linkno,
+                drtioaux::send_link(linkno,
                     &drtioaux::Packet::ResetRequest { phy: false }).unwrap();
-                match drtioaux::hw::recv_timeout_link(linkno, None) {
+                match drtioaux::recv_timeout_link(linkno, None) {
                     Ok(drtioaux::Packet::ResetAck) => (),
                     Ok(_) => error!("[LINK#{}] reset failed, received unexpected aux packet", linkno),
                     Err(e) => error!("[LINK#{}] reset failed, aux packet error ({})", linkno, e)

artiq/firmware/satman/Cargo.toml

@@ -17,4 +17,3 @@ build_artiq = { path = "../libbuild_artiq" }
 log = { version = "0.4", default-features = false }
 board = { path = "../libboard", features = ["uart_console", "log"] }
 board_artiq = { path = "../libboard_artiq" }
-drtioaux = { path = "../libdrtioaux" }

artiq/firmware/satman/main.rs

@@ -6,10 +6,9 @@ extern crate log;
 #[macro_use]
 extern crate board;
 extern crate board_artiq;
-extern crate drtioaux;
 
 use board::csr;
-use board_artiq::{i2c, spi, si5324};
+use board_artiq::{i2c, spi, si5324, drtioaux};
 #[cfg(has_serwb_phy_amc)]
 use board_artiq::serwb;
 #[cfg(has_hmc830_7043)]
@@ -27,12 +26,12 @@ fn drtio_reset_phy(reset: bool) {
     }
 }
 
-fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
+fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::Result<()> {
     // In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
     // and u16 otherwise; hence the `as _` conversion.
     match packet {
         drtioaux::Packet::EchoRequest =>
-            drtioaux::hw::send_link(0, &drtioaux::Packet::EchoReply),
+            drtioaux::send_link(0, &drtioaux::Packet::EchoReply),
         drtioaux::Packet::ResetRequest { phy } => {
             if phy {
                 drtio_reset_phy(true);
@@ -41,7 +40,7 @@ fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
                 drtio_reset(true);
                 drtio_reset(false);
             }
-            drtioaux::hw::send_link(0, &drtioaux::Packet::ResetAck)
+            drtioaux::send_link(0, &drtioaux::Packet::ResetAck)
         },
 
         drtioaux::Packet::RtioErrorRequest => {
@@ -55,7 +54,7 @@ fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
                     channel = (csr::DRTIO[0].sequence_error_channel_read)();
                     (csr::DRTIO[0].rtio_error_write)(1);
                 }
-                drtioaux::hw::send_link(0,
+                drtioaux::send_link(0,
                     &drtioaux::Packet::RtioErrorSequenceErrorReply { channel })
             } else if errors & 2 != 0 {
                 let channel;
@@ -63,7 +62,7 @@ fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
                     channel = (csr::DRTIO[0].collision_channel_read)();
                     (csr::DRTIO[0].rtio_error_write)(2);
                 }
-                drtioaux::hw::send_link(0,
+                drtioaux::send_link(0,
                     &drtioaux::Packet::RtioErrorCollisionReply { channel })
             } else if errors & 4 != 0 {
                 let channel;
@@ -71,11 +70,11 @@ fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
                     channel = (board::csr::DRTIO[0].busy_channel_read)();
                     (board::csr::DRTIO[0].rtio_error_write)(4);
                 }
-                drtioaux::hw::send_link(0,
+                drtioaux::send_link(0,
                     &drtioaux::Packet::RtioErrorBusyReply { channel })
             }
             else {
-                drtioaux::hw::send_link(0, &drtioaux::Packet::RtioNoErrorReply)
+                drtioaux::send_link(0, &drtioaux::Packet::RtioNoErrorReply)
             }
         }
 
@@ -93,7 +92,7 @@ fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
                 value = 0;
             }
             let reply = drtioaux::Packet::MonitorReply { value: value as u32 };
-            drtioaux::hw::send_link(0, &reply)
+            drtioaux::send_link(0, &reply)
         },
         drtioaux::Packet::InjectionRequest { channel, overrd, value } => {
             #[cfg(has_rtio_moninj)]
@@ -116,53 +115,53 @@ fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
             {
                 value = 0;
             }
-            drtioaux::hw::send_link(0, &drtioaux::Packet::InjectionStatusReply { value: value })
+            drtioaux::send_link(0, &drtioaux::Packet::InjectionStatusReply { value: value })
         },
 
         drtioaux::Packet::I2cStartRequest { busno } => {
             let succeeded = i2c::start(busno).is_ok();
-            drtioaux::hw::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
+            drtioaux::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
         }
         drtioaux::Packet::I2cRestartRequest { busno } => {
             let succeeded = i2c::restart(busno).is_ok();
-            drtioaux::hw::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
+            drtioaux::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
         }
         drtioaux::Packet::I2cStopRequest { busno } => {
             let succeeded = i2c::stop(busno).is_ok();
-            drtioaux::hw::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
+            drtioaux::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
         }
         drtioaux::Packet::I2cWriteRequest { busno, data } => {
             match i2c::write(busno, data) {
-                Ok(ack) => drtioaux::hw::send_link(0,
+                Ok(ack) => drtioaux::send_link(0,
                     &drtioaux::Packet::I2cWriteReply { succeeded: true, ack: ack }),
-                Err(_) => drtioaux::hw::send_link(0,
+                Err(_) => drtioaux::send_link(0,
                     &drtioaux::Packet::I2cWriteReply { succeeded: false, ack: false })
             }
         }
         drtioaux::Packet::I2cReadRequest { busno, ack } => {
             match i2c::read(busno, ack) {
-                Ok(data) => drtioaux::hw::send_link(0,
+                Ok(data) => drtioaux::send_link(0,
                     &drtioaux::Packet::I2cReadReply { succeeded: true, data: data }),
-                Err(_) => drtioaux::hw::send_link(0,
+                Err(_) => drtioaux::send_link(0,
                     &drtioaux::Packet::I2cReadReply { succeeded: false, data: 0xff })
             }
         }
 
         drtioaux::Packet::SpiSetConfigRequest { busno, flags, length, div, cs } => {
             let succeeded = spi::set_config(busno, flags, length, div, cs).is_ok();
-            drtioaux::hw::send_link(0,
+            drtioaux::send_link(0,
                 &drtioaux::Packet::SpiBasicReply { succeeded: succeeded })
         },
         drtioaux::Packet::SpiWriteRequest { busno, data } => {
             let succeeded = spi::write(busno, data).is_ok();
-            drtioaux::hw::send_link(0,
+            drtioaux::send_link(0,
                 &drtioaux::Packet::SpiBasicReply { succeeded: succeeded })
         }
         drtioaux::Packet::SpiReadRequest { busno } => {
             match spi::read(busno) {
-                Ok(data) => drtioaux::hw::send_link(0,
+                Ok(data) => drtioaux::send_link(0,
                     &drtioaux::Packet::SpiReadReply { succeeded: true, data: data }),
-                Err(_) => drtioaux::hw::send_link(0,
+                Err(_) => drtioaux::send_link(0,
                     &drtioaux::Packet::SpiReadReply { succeeded: false, data: 0 })
             }
         }
@@ -176,7 +175,7 @@ fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
 
 fn process_aux_packets() {
     let result =
-        drtioaux::hw::recv_link(0).and_then(|packet| {
+        drtioaux::recv_link(0).and_then(|packet| {
             if let Some(packet) = packet {
                 process_aux_packet(packet)
             } else {
@@ -267,7 +266,7 @@ pub extern fn main() -> i32 {
         info!("link is up, switching to recovered clock");
         si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
         si5324::siphaser::calibrate_skew(32).expect("failed to calibrate skew");
-        drtioaux::hw::reset(0);
+        drtioaux::reset(0);
         drtio_reset(false);
         drtio_reset_phy(false);
         while drtio_link_rx_up() {