forked from M-Labs/artiq
rtio: fix DMA data MSB and stop signaling, self-checking unittest
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43a5455058
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75ea13748a
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@ -153,13 +153,16 @@ class RecordConverter(Module):
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self.end_marker_found = Signal()
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self.flush = Signal()
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hdrlen = (layout_len(record_layout) - 512)//8
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record_raw = Record(record_layout)
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self.comb += [
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record_raw.raw_bits().eq(stream_slicer.source),
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self.source.channel.eq(record_raw.channel),
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self.source.timestamp.eq(record_raw.timestamp),
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self.source.address.eq(record_raw.address),
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self.source.data.eq(record_raw.data)
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Case(record_raw.length,
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{hdrlen+i: self.source.data.eq(record_raw.data[:i*8])
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for i in range(1, 512//8+1)}),
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]
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fsm = FSM(reset_state="FLOWING")
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@ -328,9 +331,10 @@ class CRIMaster(Module, AutoCSR):
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class DMA(Module):
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def __init__(self, membus):
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self.enable = CSRStorage(write_from_dev=True)
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self.enable = CSR()
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self.submodules.dma = DMAReader(membus, self.enable.storage)
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flow_enable = Signal()
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self.submodules.dma = DMAReader(membus, flow_enable)
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self.submodules.slicer = RecordSlicer(len(membus.dat_w))
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self.submodules.time_offset = TimeOffset()
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self.submodules.cri_master = CRIMaster()
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@ -345,24 +349,29 @@ class DMA(Module):
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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self.comb += self.enable.dat_w.eq(0)
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fsm.act("IDLE",
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If(self.enable.storage, NextState("FLOWING"))
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If(self.enable.re & self.enable.r, NextState("FLOWING"))
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)
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fsm.act("FLOWING",
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If(self.slicer.end_marker_found, self.enable.we.eq(1)),
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If(~self.enable.storage,
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self.slicer.flush.eq(1),
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NextState("WAIT_EOP")
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self.enable.w.eq(1),
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flow_enable.eq(1),
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If(self.slicer.end_marker_found | (self.enable.re & ~self.enable.r),
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NextState("FLUSH")
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)
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)
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fsm.act("FLUSH",
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self.enable.w.eq(1),
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self.slicer.flush.eq(1),
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NextState("WAIT_EOP")
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)
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fsm.act("WAIT_EOP",
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self.enable.w.eq(1),
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If(self.cri_master.sink.stb & self.cri_master.sink.ack & self.cri_master.sink.eop,
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NextState("WAIT_CRI_MASTER")
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)
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)
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fsm.act("WAIT_CRI_MASTER",
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self.enable.w.eq(1),
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If(~self.cri_master.busy, NextState("IDLE"))
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)
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@ -3,7 +3,7 @@ import unittest
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from migen import *
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from misoc.interconnect import wishbone
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from artiq.gateware.rtio import dma
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from artiq.gateware.rtio import dma, cri
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def encode_n(n, min_length, max_length):
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@ -36,34 +36,54 @@ def pack(x, size):
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return r
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test_writes = [
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(0x01, 0x23, 0x12, 0x33),
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(0x901, 0x902, 0x911, 0xeeeeeeeeeeeeeefffffffffffffffffffffffffffffff28888177772736646717738388488),
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(0x81, 0x288, 0x88, 0x8888)
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]
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class TB(Module):
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def __init__(self, ws):
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sequence = []
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sequence += encode_record(0x01, 0x23, 0x12, 0x33)
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sequence += encode_record(0x901, 0x902, 0x911, 0xeeeeeeeeeeeeeefffffffffffffffffffffffffffffff28888177772736646717738388488)
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sequence += encode_record(0x81, 0x288, 0x88, 0x8888)
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sequence = [b for write in test_writes for b in encode_record(*write)]
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sequence.append(0)
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self.sequence = pack(sequence, ws)
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sequence = pack(sequence, ws)
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bus = wishbone.Interface(ws*8)
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self.submodules.memory = wishbone.SRAM(
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1024, init=self.sequence, bus=bus)
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1024, init=sequence, bus=bus)
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self.submodules.dut = dma.DMA(bus)
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# TODO: remove this hack when misoc supports csr write_from_dev simulation
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self.sync += If(self.dut.enable.we, self.dut.enable.storage.eq(self.dut.enable.dat_w))
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class TestDMA(unittest.TestCase):
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def test_dma(self):
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def test_dma_noerror(self):
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ws = 64
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tb = TB(ws)
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def gen():
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def do_dma():
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for i in range(2):
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yield from tb.dut.enable.write(1)
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for i in range(30):
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print((yield from tb.dut.enable.read()))
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yield
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while ((yield from tb.dut.enable.read())):
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yield
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run_simulation(tb, gen(), vcd_name="foo.vcd")
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received = []
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@passive
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def rtio_sim():
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dut_cri = tb.dut.cri
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while True:
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cmd = yield dut_cri.cmd
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if cmd == cri.commands["nop"]:
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pass
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elif cmd == cri.commands["write"]:
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channel = yield dut_cri.chan_sel
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timestamp = yield dut_cri.o_timestamp
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address = yield dut_cri.o_address
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data = yield dut_cri.o_data
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received.append((channel, timestamp, address, data))
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else:
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self.fail("unexpected RTIO command")
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yield
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run_simulation(tb, [do_dma(), rtio_sim()])
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self.assertEqual(received, test_writes*2)
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