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ad991[02]: sysclk can be 1 GHz

This commit is contained in:
Robert Jördens 2018-02-16 17:51:57 +00:00
parent 6ae1cc20aa
commit 75c89422c9
2 changed files with 2 additions and 2 deletions
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2
artiq/coredevice/ad9910.py
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@ -62,7 +62,7 @@ class AD9910:
self.pll_n = pll_n
assert self.cpld.refclk < 60e6
self.sysclk = self.cpld.refclk*pll_n/4 # Urukul clock fanout divider
assert self.sysclk < 1e9
assert self.sysclk <= 1e9
self.ftw_per_hz = 1./self.sysclk*(int64(1) << 32)
assert 0 <= pll_vco <= 5
vco_min, vco_max = [(370, 510), (420, 590), (500, 700),

2
artiq/coredevice/ad9912.py
View File

@ -35,7 +35,7 @@ class AD9912:
self.sw = dmgr.get(sw_device)
self.pll_n = pll_n
self.sysclk = self.cpld.refclk*pll_n
assert self.sysclk < 1e9
assert self.sysclk <= 1e9
self.ftw_per_hz = 1/self.sysclk*(int64(1) << 48)
@kernel