From 758b97426a7db79ee7c4a4db276dec636a684050 Mon Sep 17 00:00:00 2001 From: linuswck Date: Tue, 1 Aug 2023 17:39:21 +0800 Subject: [PATCH] Bootloader: SDRAM patch for EFC - Modification of the CFG flag ensure EFC to initialize DDRPHY correctly Note that Kasli and EFC share the same model of SDRAM --- artiq/firmware/libboard_misoc/sdram.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/firmware/libboard_misoc/sdram.rs b/artiq/firmware/libboard_misoc/sdram.rs index 8130416bd..b3839eaf6 100644 --- a/artiq/firmware/libboard_misoc/sdram.rs +++ b/artiq/firmware/libboard_misoc/sdram.rs @@ -217,7 +217,7 @@ mod ddr { ddrphy::dly_sel_write(1 << (DQS_SIGNAL_COUNT - n - 1)); ddrphy::rdly_dq_rst_write(1); - #[cfg(soc_platform = "kasli")] + #[cfg(any(soc_platform = "kasli", soc_platform = "efc"))] { for _ in 0..3 { ddrphy::rdly_dq_bitslip_write(1); @@ -308,7 +308,7 @@ mod ddr { let mut max_seen_valid = 0; ddrphy::rdly_dq_rst_write(1); - #[cfg(soc_platform = "kasli")] + #[cfg(any(soc_platform = "kasli", soc_platform = "efc"))] { for _ in 0..3 { ddrphy::rdly_dq_bitslip_write(1); @@ -371,7 +371,7 @@ mod ddr { // Set delay to the middle ddrphy::rdly_dq_rst_write(1); - #[cfg(soc_platform = "kasli")] + #[cfg(any(soc_platform = "kasli", soc_platform = "efc"))] { for _ in 0..3 { ddrphy::rdly_dq_bitslip_write(1);