forked from M-Labs/artiq
suservo: clkout and sdo[b-d] are inverted
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04240cdc08
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74c0b4452b
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@ -16,20 +16,23 @@ class SamplerPads(Module):
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dn = platform.request("{}_adc_data_n".format(eem))
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clkout_se = Signal()
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clkout_inv = Signal()
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sck = Signal()
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self.specials += [
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DifferentialOutput(self.cnv, cnv.p, cnv.n),
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DifferentialOutput(1, sdr.p, sdr.n),
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DDROutput(0, self.sck_en, sck, ClockSignal("rio_phy")),
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DDROutput(self.sck_en, 0, sck, ClockSignal("rio_phy")),
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DifferentialOutput(sck, spip.clk, spin.clk),
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DifferentialInput(dp.clkout, dn.clkout, clkout_se),
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Instance("BUFR", i_I=clkout_se, o_O=self.clkout)
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# FIXME (hardware): CLKOUT is inverted
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# (Sampler v2.0, v2.1) out on rising, in on falling
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Instance("BUFR", i_I=clkout_se, o_O=clkout_inv)
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]
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self.comb += self.clkout.eq(~clkout_inv)
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# here to be early before the input delays below to have the clock
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# available
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self.clkout_p = dp.clkout # availabel for false paths
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# define clock here before the input delays below
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self.clkout_p = dp.clkout # available for false paths
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platform.add_platform_command(
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"create_clock -name {clk} -period 8 [get_nets {clk}]",
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clk=dp.clkout)
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@ -37,17 +40,20 @@ class SamplerPads(Module):
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for i in "abcd":
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sdo = Signal()
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setattr(self, "sdo{}".format(i), sdo)
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if i != "a":
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# FIXME (hardware): sdob, sdoc, sdod are inverted
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# (Sampler v2.0, v2.1)
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sdo, sdo_inv = Signal(), sdo
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self.comb += sdo_inv.eq(~sdo)
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sdop = getattr(dp, "sdo{}".format(i))
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sdon = getattr(dn, "sdo{}".format(i))
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self.specials += [
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DifferentialInput(sdop, sdon, sdo),
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]
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# 8, -0+1.5 hold (t_HSDO_DDR), -0.5+0.5 skew
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# -0+1.5 hold (t_HSDO_SDR), -0.5+0.5 skew
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platform.add_platform_command(
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"set_input_delay -clock {clk} "
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"-max 2 [get_ports {port}] -clock_fall\n"
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"set_input_delay -clock {clk} "
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"-min -0.5 [get_ports {port}] -clock_fall",
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"set_input_delay -clock {clk} -max 2 [get_ports {port}]\n"
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"set_input_delay -clock {clk} -min -0.5 [get_ports {port}]",
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clk=dp.clkout, port=sdop)
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