forked from M-Labs/artiq
firmware: make read leveling robust for KUS SDRAM
Increases the initial delay step into the valid read window as with the original delay I was not getting out of the noisy transition window, as evidenced by seeing read delay windows of only 8 LSB ~10% of the time, leading to failing memory tests
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@ -207,7 +207,7 @@ mod ddr {
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// Get a bit further into the working zone
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#[cfg(kusddrphy)]
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for _ in 0..8 {
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for _ in 0..16 {
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delay.set(delay.get() + 1);
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ddrphy::rdly_dq_inc_write(1);
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}
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