From 73f0de7c79a34e07235de861663e4e6960a1c034 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 20 Sep 2018 11:15:45 +0800 Subject: [PATCH] sayma: DRTIO master fixes --- artiq/gateware/targets/sayma_amc.py | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 0c731002a..499cd55ca 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -314,6 +314,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon): coreaux.bus) self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None + self.config["HAS_DRTIO_ROUTING"] = None self.add_csr_group("drtio", drtio_csr_group) self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) @@ -379,8 +380,11 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon): self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( [self.rtio.cri, self.rtio_dma.cri], - [self.rtio_core.cri] + drtio_cri) + [self.rtio_core.cri] + drtio_cri, + enable_routing=True) self.register_kernel_cpu_csrdevice("cri_con") + self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) + self.csr_devices.append("routing_table") self.submodules.sysref_sampler = jesd204_tools.SysrefSampler( self.rtio_tsc.coarse_ts, self.ad9154_crg.jref) @@ -469,6 +473,7 @@ class Master(MiniSoC, AMPSoC): coreaux.bus) self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800) self.config["HAS_DRTIO"] = None + self.config["HAS_DRTIO_ROUTING"] = None self.add_csr_group("drtio", drtio_csr_group) self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) @@ -532,8 +537,11 @@ class Master(MiniSoC, AMPSoC): self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( [self.rtio.cri, self.rtio_dma.cri], - [self.rtio_core.cri] + drtio_cri) + [self.rtio_core.cri] + drtio_cri, + enable_routing=True) self.register_kernel_cpu_csrdevice("cri_con") + self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) + self.csr_devices.append("routing_table") class Satellite(BaseSoC, RTMCommon):