doc: various cleanups

artiq/devices/dds_core.py

@@ -6,10 +6,9 @@ from artiq.devices import rtio_core
 class DDS(AutoContext):
     """Core device Direct Digital Synthesis (DDS) driver.
 
-    This driver controls DDS devices managed directly by the core device's
-    runtime. It also uses a RTIO channel (through
-    :class:`artiq.devices.rtio_core.RTIOOut`) to control a RF switch that
-    gates the output of the DDS device.
+    Controls DDS devices managed directly by the core device's runtime. It also
+    uses a RTIO channel (through :class:`artiq.devices.rtio_core.RTIOOut`) to
+    control a RF switch that gates the output of the DDS device.
 
     :param dds_sysclk: DDS system frequency, used for computing the frequency
         tuning words.

artiq/devices/rtio_core.py

@@ -28,8 +28,8 @@ class _RTIOBase(AutoContext):
 class RTIOOut(_RTIOBase):
     """RTIO output driver.
 
-    This driver configures the corresponding RTIO channel as output on the core
-    device and provides functions to set its level.
+    Configures the corresponding RTIO channel as output on the core device and
+    provides functions to set its level.
 
     This driver supports zero-length transition suppression. For example, if
     two pulses are emitted back-to-back with no delay between them, they will
@@ -82,9 +82,9 @@ class RTIOOut(_RTIOBase):
 class RTIOIn(_RTIOBase):
     """RTIO input driver.
 
-    This driver configures the corresponding RTIO channel as input on the core
-    device and provides functions to analyze the incoming signal, with
-    real-time gating to prevent overflows.
+    Configures the corresponding RTIO channel as input on the core device and
+    provides functions to analyze the incoming signal, with real-time gating
+    to prevent overflows.
 
     :param core: core device
     :param channel: channel number

artiq/language/core.py

@@ -127,7 +127,7 @@ class AutoContext:
     ...         self.exp2 = SubExperiment(self, bar=self.bar2)
     ...         self.exp3 = SubExperiment(self, bar=self.bar2 + self.offset)
     ...
-    >>>     def run():
+    ...     def run():
     ...         self.exp1.run()
     ...         self.exp2.run()
     ...         self.exp3.run()

doc/manual/installing.rst

@@ -7,10 +7,11 @@ Preparing the core device FPGA board
 You may skip those steps if the board is already flashed.
 
 You will need:
-  * FPGA vendor tools (e.g. Xilinx ISE or Vivado)
-  * OpenRISC GCC/binutils toolchain (or1k-elf-...)
-  * Python 3.3+
-  * Migen and MiSoC (http://m-labs.hk/gateware.html)
+
+* FPGA vendor tools (e.g. Xilinx ISE or Vivado)
+* OpenRISC GCC/binutils toolchain (or1k-elf-...)
+* Python 3.3+
+* Migen and MiSoC (http://m-labs.hk/gateware.html)
 
 After these components are installed, build and flash the bitstream and BIOS by running `from the MiSoC top-level directory`: ::
 
@@ -74,4 +75,3 @@ You can then install ARTIQ itself: ::
     sudo python setup.py
 
 Alternatively, you can simply add the ARTIQ directory to your ``PYTHONPATH`` environment variable. The advantage of this technique is that you will not need to reinstall ARTIQ when modifying or upgrading it, which is useful during development.
-