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doc: various cleanups

This commit is contained in:
Sebastien Bourdeauducq 2014-09-30 18:10:40 +08:00
parent cb036a30c7
commit 73d0a84b44
6 changed files with 122 additions and 123 deletions
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7
artiq/devices/dds_core.py
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@ -6,10 +6,9 @@ from artiq.devices import rtio_core
class DDS(AutoContext): class DDS(AutoContext):
"""Core device Direct Digital Synthesis (DDS) driver. """Core device Direct Digital Synthesis (DDS) driver.
This driver controls DDS devices managed directly by the core device's Controls DDS devices managed directly by the core device's runtime. It also
runtime. It also uses a RTIO channel (through uses a RTIO channel (through :class:`artiq.devices.rtio_core.RTIOOut`) to
:class:`artiq.devices.rtio_core.RTIOOut`) to control a RF switch that control a RF switch that gates the output of the DDS device.
gates the output of the DDS device.
:param dds_sysclk: DDS system frequency, used for computing the frequency :param dds_sysclk: DDS system frequency, used for computing the frequency
tuning words. tuning words.

10
artiq/devices/rtio_core.py
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@ -28,8 +28,8 @@ class _RTIOBase(AutoContext):
class RTIOOut(_RTIOBase): class RTIOOut(_RTIOBase):
"""RTIO output driver. """RTIO output driver.
This driver configures the corresponding RTIO channel as output on the core Configures the corresponding RTIO channel as output on the core device and
device and provides functions to set its level. provides functions to set its level.
This driver supports zero-length transition suppression. For example, if This driver supports zero-length transition suppression. For example, if
two pulses are emitted back-to-back with no delay between them, they will two pulses are emitted back-to-back with no delay between them, they will
@ -82,9 +82,9 @@ class RTIOOut(_RTIOBase):
class RTIOIn(_RTIOBase): class RTIOIn(_RTIOBase):
"""RTIO input driver. """RTIO input driver.
This driver configures the corresponding RTIO channel as input on the core Configures the corresponding RTIO channel as input on the core device and
device and provides functions to analyze the incoming signal, with provides functions to analyze the incoming signal, with real-time gating
real-time gating to prevent overflows. to prevent overflows.
:param core: core device :param core: core device
:param channel: channel number :param channel: channel number

2
artiq/language/core.py
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@ -127,7 +127,7 @@ class AutoContext:
... self.exp2 = SubExperiment(self, bar=self.bar2) ... self.exp2 = SubExperiment(self, bar=self.bar2)
... self.exp3 = SubExperiment(self, bar=self.bar2 + self.offset) ... self.exp3 = SubExperiment(self, bar=self.bar2 + self.offset)
... ...
>>> def run(): ... def run():
... self.exp1.run() ... self.exp1.run()
... self.exp2.run() ... self.exp2.run()
... self.exp3.run() ... self.exp3.run()

2
doc/manual/installing.rst
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@ -7,6 +7,7 @@ Preparing the core device FPGA board
You may skip those steps if the board is already flashed. You may skip those steps if the board is already flashed.
You will need: You will need:
* FPGA vendor tools (e.g. Xilinx ISE or Vivado) * FPGA vendor tools (e.g. Xilinx ISE or Vivado)
* OpenRISC GCC/binutils toolchain (or1k-elf-...) * OpenRISC GCC/binutils toolchain (or1k-elf-...)
* Python 3.3+ * Python 3.3+
@ -74,4 +75,3 @@ You can then install ARTIQ itself: ::
sudo python setup.py sudo python setup.py
Alternatively, you can simply add the ARTIQ directory to your ``PYTHONPATH`` environment variable. The advantage of this technique is that you will not need to reinstall ARTIQ when modifying or upgrading it, which is useful during development. Alternatively, you can simply add the ARTIQ directory to your ``PYTHONPATH`` environment variable. The advantage of this technique is that you will not need to reinstall ARTIQ when modifying or upgrading it, which is useful during development.