forked from M-Labs/artiq
spi: expose more documentation on chaining transfers
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@ -38,6 +38,21 @@ class SPIMaster:
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* If desired, :meth:`write` ``data`` queuing the next
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(possibly chained) transfer.
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**Notes**:
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* In order to chain a transfer onto an in-flight transfer without
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deasserting ``cs`` in between, the second :meth:`write` needs to
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happen strictly later than ``2*ref_period_mu`` (two coarse RTIO
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cycles) but strictly earlier than ``xfer_period_mu + write_period_mu``
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after the first. Note that :meth:`write` already applies a delay of
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``xfer_period_mu + write_period_mu``.
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* A full transfer takes ``write_period_mu + xfer_period_mu``.
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* Chained transfers can happen every ``xfer_period_mu``.
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* Read data is available every ``xfer_period_mu`` starting
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a bit after xfer_period_mu (depending on ``clk_phase``).
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* As a consequence, in order to chain transfers together, new data must
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be written before the pending transfer's read data becomes available.
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:param channel: RTIO channel number of the SPI bus to control.
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"""
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def __init__(self, dmgr, channel, core_device="core"):
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@ -48,13 +63,6 @@ class SPIMaster:
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self.write_period_mu = int(0, 64)
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self.read_period_mu = int(0, 64)
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self.xfer_period_mu = int(0, 64)
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# A full transfer takes write_period_mu + xfer_period_mu.
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# Chained transfers can happen every xfer_period_mu.
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# The second transfer of a chain can be written 2*ref_period_mu
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# after the first. Read data is available every xfer_period_mu starting
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# a bit after xfer_period_mu (depending on clk_phase).
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# To chain transfers together, new data must be written before
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# pending transfer's read data becomes available.
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@portable
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def frequency_to_div(self, f):
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