forked from M-Labs/artiq
drtio: fix Sayma after 83abdd28
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f5831af535
commit
7376ab0ff8
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@ -290,14 +290,15 @@ class Master(MiniSoC, AMPSoC):
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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self.submodules.transceiver = gth_ultrascale.GTH(
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("si5324_clkout"),
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data_pads=[platform.request("sfp", 0)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
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DRTIOMaster(self.transceiver.channels[0]))
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DRTIOMaster(self.drtio_transceiver.channels[0]))
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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@ -307,7 +308,7 @@ class Master(MiniSoC, AMPSoC):
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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rtio_clk_period = 1e9/rtio_clk_freq
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for gth in self.transceiver.gths:
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for gth in self.drtio_transceiver.gths:
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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@ -390,14 +391,15 @@ class Satellite(BaseSoC):
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self.csr_devices.append("rtio_moninj")
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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self.submodules.transceiver = gth_ultrascale.GTH(
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("si5324_clkout"),
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data_pads=[platform.request("sfp", 0)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.drtio0 = rx0(DRTIOSatellite(
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self.transceiver.channels[0], rtio_channels))
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self.drtio_transceiver.channels[0], rtio_channels))
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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@ -422,7 +424,7 @@ class Satellite(BaseSoC):
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self.config["HAS_SI5324"] = None
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rtio_clk_period = 1e9/rtio_clk_freq
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gth = self.transceiver.gths[0]
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gth = self.drtio_transceiver.gths[0]
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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