forked from M-Labs/artiq
serwb: move common datapath code to datapath.py, simplify flow control
This commit is contained in:
Florent Kermarrec
parent
89797d08ed
commit
7296a76f18
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@ -0,0 +1,198 @@
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from migen import *
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from migen.genlib.io import *
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from migen.genlib.misc import BitSlip, WaitTimer
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from misoc.interconnect import stream
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from misoc.cores.code_8b10b import Encoder, Decoder
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from artiq.gateware.serwb.scrambler import Scrambler, Descrambler
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def K(x, y):
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return (y << 5) | x
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class _8b10bEncoder(Module):
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def __init__(self):
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self.sink = sink = stream.Endpoint([("d", 32), ("k", 4)])
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self.source = source = stream.Endpoint([("data", 40)])
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# # #
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encoder = CEInserter()(Encoder(4, True))
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self.submodules += encoder
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# control
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self.comb += [
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source.stb.eq(sink.stb),
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sink.ack.eq(source.ack),
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encoder.ce.eq(source.stb & source.ack)
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]
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# datapath
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for i in range(4):
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self.comb += [
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encoder.k[i].eq(sink.k[i]),
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encoder.d[i].eq(sink.d[8*i:8*(i+1)]),
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source.data[10*i:10*(i+1)].eq(encoder.output[i])
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]
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class _8b10bDecoder(Module):
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def __init__(self):
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self.sink = sink = stream.Endpoint([("data", 40)])
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self.source = source = stream.Endpoint([("d", 32), ("k", 4)])
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# # #
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decoders = [CEInserter()(Decoder(True)) for _ in range(4)]
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self.submodules += decoders
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# control
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self.comb += [
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source.stb.eq(sink.stb),
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sink.ack.eq(source.ack)
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]
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self.comb += [decoders[i].ce.eq(source.stb & source.ack) for i in range(4)]
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# datapath
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for i in range(4):
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self.comb += [
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decoders[i].input.eq(sink.data[10*i:10*(i+1)]),
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source.k[i].eq(decoders[i].k),
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source.d[8*i:8*(i+1)].eq(decoders[i].d)
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]
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class _Bitslip(Module):
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def __init__(self):
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self.value = value = Signal(6)
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self.sink = sink = stream.Endpoint([("data", 40)])
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self.source = source = stream.Endpoint([("data", 40)])
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# # #
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bitslip = CEInserter()(BitSlip(40))
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self.submodules += bitslip
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# control
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self.comb += [
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source.stb.eq(sink.stb),
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sink.ack.eq(source.ack),
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bitslip.value.eq(value),
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bitslip.ce.eq(source.stb & source.ack)
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]
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# datapath
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self.comb += [
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bitslip.i.eq(sink.data),
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source.data.eq(bitslip.o)
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]
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class TXDatapath(Module):
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def __init__(self, phy_dw, with_scrambling=True):
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self.idle = idle = Signal()
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self.comma = comma = Signal()
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self.sink = sink = stream.Endpoint([("data", 32)])
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self.source = source = stream.Endpoint([("data", phy_dw)])
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# # #
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# scrambler
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if with_scrambling:
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self.submodules.scrambler = scrambler = Scrambler()
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# line coding
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self.submodules.encoder = encoder = _8b10bEncoder()
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# converter
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self.submodules.converter = converter = stream.Converter(40, phy_dw)
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# dataflow
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if with_scrambling:
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self.comb += [
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sink.connect(scrambler.sink),
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If(comma,
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encoder.sink.stb.eq(1),
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encoder.sink.k.eq(1),
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encoder.sink.d.eq(K(28,5))
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).Else(
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scrambler.source.connect(encoder.sink)
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)
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]
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else:
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self.comb += [
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If(comma,
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encoder.sink.stb.eq(1),
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encoder.sink.k.eq(1),
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encoder.sink.d.eq(K(28,5))
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).Else(
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sink.connect(encoder.sink, omit={"data"}),
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encoder.sink.d.eq(sink.data)
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),
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]
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self.comb += [
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If(idle,
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converter.sink.stb.eq(1),
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converter.sink.data.eq(0)
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).Else(
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encoder.source.connect(converter.sink),
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),
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converter.source.connect(source)
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]
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class RXDatapath(Module):
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def __init__(self, phy_dw, with_scrambling=True):
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self.bitslip_value = bitslip_value = Signal(6)
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self.sink = sink = stream.Endpoint([("data", phy_dw)])
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self.source = source = stream.Endpoint([("data", 32)])
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self.idle = idle = Signal()
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self.comma = comma = Signal()
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# # #
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# converter
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self.submodules.converter = converter = stream.Converter(phy_dw, 40)
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# bitslip
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self.submodules.bitslip = bitslip = _Bitslip()
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self.comb += bitslip.value.eq(bitslip_value)
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# line coding
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self.submodules.decoder = decoder = _8b10bDecoder()
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# descrambler
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if with_scrambling:
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self.submodules.descrambler = descrambler = Descrambler()
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# dataflow
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self.comb += [
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sink.connect(converter.sink),
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converter.source.connect(bitslip.sink),
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bitslip.source.connect(decoder.sink)
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]
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if with_scrambling:
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self.comb += [
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decoder.source.connect(descrambler.sink),
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descrambler.source.connect(source)
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]
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else:
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self.comb += [
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decoder.source.connect(source, omit={"d", "k"}),
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source.data.eq(decoder.source.d)
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]
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# idle decoding
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idle_timer = WaitTimer(256)
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self.submodules += idle_timer
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self.comb += [
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idle_timer.wait.eq(1),
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idle.eq(idle_timer.done & ((converter.source.data == 0) | (converter.source.data == (2**40-1))))
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]
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# comma decoding
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self.sync += \
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If(decoder.source.stb,
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comma.eq((decoder.source.k == 1) & (decoder.source.d == K(28, 5)))
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)
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@ -4,13 +4,8 @@ from migen.genlib.misc import BitSlip, WaitTimer
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from misoc.interconnect import stream
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from misoc.interconnect.csr import *
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from misoc.cores.code_8b10b import Encoder, Decoder
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from artiq.gateware.serwb.scrambler import Scrambler, Descrambler
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def K(x, y):
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return (y << 5) | x
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from artiq.gateware.serwb.datapath import TXDatapath, RXDatapath
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class _SerdesClocking(Module):
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@ -30,59 +25,33 @@ class _SerdesClocking(Module):
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class _SerdesTX(Module):
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def __init__(self, pads, mode="master"):
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def __init__(self, pads):
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# Control
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self.idle = idle = Signal()
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self.comma = comma = Signal()
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# Datapath
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self.ce = ce = Signal()
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self.k = k = Signal(4)
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self.d = d = Signal(32)
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self.sink = sink = stream.Endpoint([("data", 32)])
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# # #
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# 8b10b encoder
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self.submodules.encoder = encoder = CEInserter()(Encoder(4, True))
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self.comb += encoder.ce.eq(ce)
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# 40 --> 1 converter
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converter = stream.Converter(40, 1)
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self.submodules += converter
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# Datapath
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self.submodules.datapath = datapath = TXDatapath(1)
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self.comb += [
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converter.sink.stb.eq(1),
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converter.source.ack.eq(1),
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# Enable pipeline when converter accepts the 40 bits
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ce.eq(converter.sink.ack),
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# If not idle, connect encoder to converter
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If(~idle,
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converter.sink.data.eq(Cat(*[encoder.output[i] for i in range(4)]))
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),
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# If comma, send K28.5
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If(comma,
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encoder.k[0].eq(1),
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encoder.d[0].eq(K(28,5)),
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# Else connect TX to encoder
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).Else(
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encoder.k[0].eq(k[0]),
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encoder.k[1].eq(k[1]),
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encoder.k[2].eq(k[2]),
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encoder.k[3].eq(k[3]),
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encoder.d[0].eq(d[0:8]),
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encoder.d[1].eq(d[8:16]),
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encoder.d[2].eq(d[16:24]),
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encoder.d[3].eq(d[24:32])
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)
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sink.connect(datapath.sink),
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datapath.source.ack.eq(1),
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datapath.idle.eq(idle),
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datapath.comma.eq(comma)
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]
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# Data output (on rising edge of sys_clk)
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# Output data (on rising edge of sys_clk)
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data = Signal()
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self.sync += data.eq(converter.source.data)
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self.sync += data.eq(datapath.source.data)
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self.specials += DifferentialOutput(data, pads.tx_p, pads.tx_n)
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class _SerdesRX(Module):
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def __init__(self, pads, mode="master"):
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def __init__(self, pads):
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# Control
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self.bitslip_value = bitslip_value = Signal(6)
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@ -91,9 +60,7 @@ class _SerdesRX(Module):
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self.comma = comma = Signal()
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# Datapath
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self.ce = ce = Signal()
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self.k = k = Signal(4)
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self.d = d = Signal(32)
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self.source = source = stream.Endpoint([("data", 32)])
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# # #
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@ -103,50 +70,15 @@ class _SerdesRX(Module):
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self.specials += DifferentialInput(pads.rx_p, pads.rx_n, data)
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self.sync += data_d.eq(data)
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# 1 --> 40 converter and bitslip
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converter = stream.Converter(1, 40)
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self.submodules += converter
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bitslip = CEInserter()(BitSlip(40))
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self.submodules += bitslip
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# Datapath
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self.submodules.datapath = datapath = RXDatapath(1)
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self.comb += [
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converter.sink.stb.eq(1),
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converter.source.ack.eq(1),
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# Enable pipeline when converter outputs the 40 bits
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ce.eq(converter.source.stb),
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# Connect input data to converter
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converter.sink.data.eq(data),
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# Connect converter to bitslip
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bitslip.ce.eq(ce),
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bitslip.value.eq(bitslip_value),
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bitslip.i.eq(converter.source.data)
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]
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# 8b10b decoder
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self.submodules.decoders = decoders = [CEInserter()(Decoder(True)) for _ in range(4)]
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self.comb += [decoders[i].ce.eq(ce) for i in range(4)]
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self.comb += [
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# Connect bitslip to decoder
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decoders[0].input.eq(bitslip.o[0:10]),
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decoders[1].input.eq(bitslip.o[10:20]),
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decoders[2].input.eq(bitslip.o[20:30]),
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decoders[3].input.eq(bitslip.o[30:40]),
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# Connect decoder to output
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self.k.eq(Cat(*[decoders[i].k for i in range(4)])),
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self.d.eq(Cat(*[decoders[i].d for i in range(4)])),
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]
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# Status
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idle_timer = WaitTimer(256)
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self.submodules += idle_timer
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self.comb += [
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idle_timer.wait.eq(1),
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self.idle.eq(idle_timer.done &
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((bitslip.o == 0) | (bitslip.o == (2**40-1)))),
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self.comma.eq(
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(decoders[0].k == 1) & (decoders[0].d == K(28,5)) &
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(decoders[1].k == 0) & (decoders[1].d == 0) &
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(decoders[2].k == 0) & (decoders[2].d == 0) &
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(decoders[3].k == 0) & (decoders[3].d == 0))
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datapath.sink.stb.eq(1),
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datapath.sink.data.eq(data_d),
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datapath.bitslip_value.eq(bitslip_value),
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datapath.source.connect(source),
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idle.eq(datapath.idle),
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comma.eq(datapath.comma)
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]
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@ -154,8 +86,8 @@ class _SerdesRX(Module):
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class _Serdes(Module):
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def __init__(self, pads, mode="master"):
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self.submodules.clocking = _SerdesClocking(pads, mode)
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self.submodules.tx = _SerdesTX(pads, mode)
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self.submodules.rx = _SerdesRX(pads, mode)
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self.submodules.tx = _SerdesTX(pads)
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self.submodules.rx = _SerdesRX(pads)
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# SERWB Master <--> Slave physical synchronization process:
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@ -378,34 +310,21 @@ class SERWBPHY(Module, AutoCSR):
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self.submodules.init = _SerdesSlaveInit(self.serdes, init_timeout)
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self.submodules.control = _SerdesControl(self.serdes, self.init, mode)
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# scrambling
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self.submodules.scrambler = scrambler = Scrambler()
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self.submodules.descrambler = descrambler = Descrambler()
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# tx dataflow
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self.comb += \
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If(self.init.ready,
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sink.connect(scrambler.sink),
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scrambler.source.ack.eq(self.serdes.tx.ce),
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If(scrambler.source.stb,
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self.serdes.tx.d.eq(scrambler.source.d),
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self.serdes.tx.k.eq(scrambler.source.k)
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)
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)
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# rx dataflow
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# tx/rx dataflow
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self.comb += [
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If(self.init.ready,
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descrambler.sink.stb.eq(self.serdes.rx.ce),
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descrambler.sink.d.eq(self.serdes.rx.d),
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descrambler.sink.k.eq(self.serdes.rx.k),
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descrambler.source.connect(source)
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sink.connect(self.serdes.tx.sink),
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self.serdes.rx.source.connect(source)
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).Else(
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self.serdes.rx.source.ack.eq(1)
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),
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# For PRBS test we are using the scrambler/descrambler as PRBS,
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# sending 0 to the scrambler and checking that descrambler
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# output is always 0.
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self.control.prbs_error.eq(
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descrambler.source.stb &
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descrambler.source.ack &
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(descrambler.source.data != 0))
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self.serdes.tx.sink.stb.eq(1) # always transmitting
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]
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# For PRBS test we are using the scrambler/descrambler as PRBS,
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# sending 0 to the scrambler and checking that descrambler
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# output is always 0.
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self.comb += self.control.prbs_error.eq(
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source.stb &
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source.ack &
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(source.data != 0))
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@ -5,9 +5,7 @@ from migen.genlib.misc import BitSlip, WaitTimer
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from misoc.interconnect import stream
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from misoc.cores.code_8b10b import Encoder, Decoder
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def K(x, y):
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return (y << 5) | x
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from artiq.gateware.serwb.datapath import TXDatapath, RXDatapath
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class _KUSerdesClocking(Module):
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@ -45,52 +43,27 @@ class _KUSerdesClocking(Module):
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class _KUSerdesTX(Module):
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def __init__(self, pads, mode="master"):
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def __init__(self, pads):
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# Control
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self.idle = idle = Signal()
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self.comma = comma = Signal()
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# Datapath
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self.ce = ce = Signal()
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self.k = k = Signal(4)
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self.d = d = Signal(32)
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self.sink = sink = stream.Endpoint([("data", 32)])
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# # #
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# 8b10b encoder
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self.submodules.encoder = encoder = CEInserter()(Encoder(4, True))
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self.comb += encoder.ce.eq(ce)
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# 40 --> 8 converter
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converter = stream.Converter(40, 8)
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self.submodules += converter
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# Datapath
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self.submodules.datapath = datapath = TXDatapath(8)
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self.comb += [
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converter.sink.stb.eq(1),
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converter.source.ack.eq(1),
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# Enable pipeline when converter accepts the 40 bits
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ce.eq(converter.sink.ack),
|
||||
# If not idle, connect encoder to converter
|
||||
If(~idle,
|
||||
converter.sink.data.eq(Cat(*[encoder.output[i] for i in range(4)]))
|
||||
),
|
||||
# If comma, send K28.5
|
||||
If(comma,
|
||||
encoder.k[0].eq(1),
|
||||
encoder.d[0].eq(K(28,5)),
|
||||
# Else connect TX to encoder
|
||||
).Else(
|
||||
encoder.k[0].eq(k[0]),
|
||||
encoder.k[1].eq(k[1]),
|
||||
encoder.k[2].eq(k[2]),
|
||||
encoder.k[3].eq(k[3]),
|
||||
encoder.d[0].eq(d[0:8]),
|
||||
encoder.d[1].eq(d[8:16]),
|
||||
encoder.d[2].eq(d[16:24]),
|
||||
encoder.d[3].eq(d[24:32])
|
||||
)
|
||||
sink.connect(datapath.sink),
|
||||
datapath.source.ack.eq(1),
|
||||
datapath.idle.eq(idle),
|
||||
datapath.comma.eq(comma)
|
||||
]
|
||||
|
||||
# Data output (DDR with sys4x)
|
||||
# Output Data(DDR with sys4x)
|
||||
data = Signal()
|
||||
self.specials += [
|
||||
Instance("OSERDESE3",
|
||||
|
|
@ -100,14 +73,14 @@ class _KUSerdesTX(Module):
|
|||
o_OQ=data,
|
||||
i_RST=ResetSignal("sys"),
|
||||
i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal("sys"),
|
||||
i_D=converter.source.data
|
||||
i_D=datapath.source.data
|
||||
),
|
||||
DifferentialOutput(data, pads.tx_p, pads.tx_n)
|
||||
]
|
||||
|
||||
|
||||
class _KUSerdesRX(Module):
|
||||
def __init__(self, pads, mode="master"):
|
||||
def __init__(self, pads):
|
||||
# Control
|
||||
self.delay_rst = Signal()
|
||||
self.delay_inc = Signal()
|
||||
|
|
@ -118,9 +91,7 @@ class _KUSerdesRX(Module):
|
|||
self.comma = comma = Signal()
|
||||
|
||||
# Datapath
|
||||
self.ce = ce = Signal()
|
||||
self.k = k = Signal(4)
|
||||
self.d = d = Signal(32)
|
||||
self.source = source = stream.Endpoint([("data", 32)])
|
||||
|
||||
# # #
|
||||
|
||||
|
|
@ -158,50 +129,15 @@ class _KUSerdesRX(Module):
|
|||
)
|
||||
]
|
||||
|
||||
# 8 --> 40 converter and bitslip
|
||||
converter = stream.Converter(8, 40)
|
||||
self.submodules += converter
|
||||
bitslip = CEInserter()(BitSlip(40))
|
||||
self.submodules += bitslip
|
||||
# Datapath
|
||||
self.submodules.datapath = datapath = RXDatapath(8)
|
||||
self.comb += [
|
||||
converter.sink.stb.eq(1),
|
||||
converter.source.ack.eq(1),
|
||||
# Enable pipeline when converter outputs the 40 bits
|
||||
ce.eq(converter.source.stb),
|
||||
# Connect input data to converter
|
||||
converter.sink.data.eq(data_deserialized),
|
||||
# Connect converter to bitslip
|
||||
bitslip.ce.eq(ce),
|
||||
bitslip.value.eq(bitslip_value),
|
||||
bitslip.i.eq(converter.source.data)
|
||||
]
|
||||
|
||||
# 8b10b decoder
|
||||
self.submodules.decoders = decoders = [CEInserter()(Decoder(True)) for _ in range(4)]
|
||||
self.comb += [decoders[i].ce.eq(ce) for i in range(4)]
|
||||
self.comb += [
|
||||
# Connect bitslip to decoder
|
||||
decoders[0].input.eq(bitslip.o[0:10]),
|
||||
decoders[1].input.eq(bitslip.o[10:20]),
|
||||
decoders[2].input.eq(bitslip.o[20:30]),
|
||||
decoders[3].input.eq(bitslip.o[30:40]),
|
||||
# Connect decoder to output
|
||||
self.k.eq(Cat(*[decoders[i].k for i in range(4)])),
|
||||
self.d.eq(Cat(*[decoders[i].d for i in range(4)])),
|
||||
]
|
||||
|
||||
# Status
|
||||
idle_timer = WaitTimer(256)
|
||||
self.submodules += idle_timer
|
||||
self.comb += [
|
||||
idle_timer.wait.eq(1),
|
||||
self.idle.eq(idle_timer.done &
|
||||
((bitslip.o == 0) | (bitslip.o == (2**40-1)))),
|
||||
self.comma.eq(
|
||||
(decoders[0].k == 1) & (decoders[0].d == K(28,5)) &
|
||||
(decoders[1].k == 0) & (decoders[1].d == 0) &
|
||||
(decoders[2].k == 0) & (decoders[2].d == 0) &
|
||||
(decoders[3].k == 0) & (decoders[3].d == 0))
|
||||
datapath.sink.stb.eq(1),
|
||||
datapath.sink.data.eq(data_deserialized),
|
||||
datapath.bitslip_value.eq(bitslip_value),
|
||||
datapath.source.connect(source),
|
||||
idle.eq(datapath.idle),
|
||||
comma.eq(datapath.comma)
|
||||
]
|
||||
|
||||
|
||||
|
|
@ -209,5 +145,5 @@ class _KUSerdesRX(Module):
|
|||
class KUSerdes(Module):
|
||||
def __init__(self, pads, mode="master"):
|
||||
self.submodules.clocking = _KUSerdesClocking(pads, mode)
|
||||
self.submodules.tx = _KUSerdesTX(pads, mode)
|
||||
self.submodules.rx = _KUSerdesRX(pads, mode)
|
||||
self.submodules.tx = _KUSerdesTX(pads)
|
||||
self.submodules.rx = _KUSerdesRX(pads)
|
||||
|
|
|
|||
|
|
@ -4,14 +4,13 @@ from migen.genlib.misc import WaitTimer
|
|||
from misoc.interconnect import stream
|
||||
from misoc.interconnect.csr import *
|
||||
|
||||
from artiq.gateware.serwb.scrambler import Scrambler, Descrambler
|
||||
from artiq.gateware.serwb.kuserdes import KUSerdes
|
||||
from artiq.gateware.serwb.s7serdes import S7Serdes
|
||||
|
||||
|
||||
# Master <--> Slave synchronization:
|
||||
# 1) Master sends idle pattern (zeroes) to reset Slave.
|
||||
# 2) Master sends K28.5 commas to allow Slave to calibrate, Slave sends idle pattern.
|
||||
# SERWB Master <--> Slave physical synchronization process:
|
||||
# 1) Master sends idle patterns (zeroes) to Slave to reset it.
|
||||
# 2) Master sends K28.5 commas to allow Slave to calibrate, Slave sends idle patterns.
|
||||
# 3) Slave sends K28.5 commas to allow Master to calibrate, Master sends K28.5 commas.
|
||||
# 4) Master stops sending K28.5 commas.
|
||||
# 5) Slave stops sending K28.5 commas.
|
||||
|
|
@ -360,34 +359,21 @@ class SERWBPHY(Module, AutoCSR):
|
|||
self.submodules.init = _SerdesSlaveInit(self.serdes, taps, init_timeout)
|
||||
self.submodules.control = _SerdesControl(self.serdes, self.init, mode)
|
||||
|
||||
# scrambling
|
||||
self.submodules.scrambler = scrambler = Scrambler()
|
||||
self.submodules.descrambler = descrambler = Descrambler()
|
||||
|
||||
# tx dataflow
|
||||
self.comb += \
|
||||
If(self.init.ready,
|
||||
sink.connect(scrambler.sink),
|
||||
scrambler.source.ack.eq(self.serdes.tx.ce),
|
||||
If(scrambler.source.stb,
|
||||
self.serdes.tx.d.eq(scrambler.source.d),
|
||||
self.serdes.tx.k.eq(scrambler.source.k)
|
||||
)
|
||||
)
|
||||
|
||||
# rx dataflow
|
||||
# tx/rx dataflow
|
||||
self.comb += [
|
||||
If(self.init.ready,
|
||||
descrambler.sink.stb.eq(self.serdes.rx.ce),
|
||||
descrambler.sink.d.eq(self.serdes.rx.d),
|
||||
descrambler.sink.k.eq(self.serdes.rx.k),
|
||||
descrambler.source.connect(source)
|
||||
sink.connect(self.serdes.tx.sink),
|
||||
self.serdes.rx.source.connect(source)
|
||||
).Else(
|
||||
self.serdes.rx.source.ack.eq(1)
|
||||
),
|
||||
# For PRBS test we are using the scrambler/descrambler as PRBS,
|
||||
# sending 0 to the scrambler and checking that descrambler
|
||||
# output is always 0.
|
||||
self.control.prbs_error.eq(
|
||||
descrambler.source.stb &
|
||||
descrambler.source.ack &
|
||||
(descrambler.source.data != 0))
|
||||
self.serdes.tx.sink.stb.eq(1) # always transmitting
|
||||
]
|
||||
|
||||
# For PRBS test we are using the scrambler/descrambler as PRBS,
|
||||
# sending 0 to the scrambler and checking that descrambler
|
||||
# output is always 0.
|
||||
self.comb += self.control.prbs_error.eq(
|
||||
source.stb &
|
||||
source.ack &
|
||||
(source.data != 0))
|
||||
|
|
|
|||
|
|
@ -5,9 +5,7 @@ from migen.genlib.misc import BitSlip, WaitTimer
|
|||
from misoc.interconnect import stream
|
||||
from misoc.cores.code_8b10b import Encoder, Decoder
|
||||
|
||||
|
||||
def K(x, y):
|
||||
return (y << 5) | x
|
||||
from artiq.gateware.serwb.datapath import TXDatapath, RXDatapath
|
||||
|
||||
|
||||
class _S7SerdesClocking(Module):
|
||||
|
|
@ -55,46 +53,20 @@ class _S7SerdesTX(Module):
|
|||
self.comma = comma = Signal()
|
||||
|
||||
# Datapath
|
||||
self.ce = ce = Signal()
|
||||
self.k = k = Signal(4)
|
||||
self.d = d = Signal(32)
|
||||
self.sink = sink = stream.Endpoint([("data", 32)])
|
||||
|
||||
# # #
|
||||
|
||||
# 8b10b encoder
|
||||
self.submodules.encoder = encoder = CEInserter()(Encoder(4, True))
|
||||
self.comb += encoder.ce.eq(ce)
|
||||
|
||||
# 40 --> 8 converter
|
||||
converter = stream.Converter(40, 8)
|
||||
self.submodules += converter
|
||||
# Datapath
|
||||
self.submodules.datapath = datapath = TXDatapath(8)
|
||||
self.comb += [
|
||||
converter.sink.stb.eq(1),
|
||||
converter.source.ack.eq(1),
|
||||
# Enable pipeline when converter accepts the 40 bits
|
||||
ce.eq(converter.sink.ack),
|
||||
# If not idle, connect encoder to converter
|
||||
If(~idle,
|
||||
converter.sink.data.eq(Cat(*[encoder.output[i] for i in range(4)]))
|
||||
),
|
||||
# If comma, send K28.5
|
||||
If(comma,
|
||||
encoder.k[0].eq(1),
|
||||
encoder.d[0].eq(K(28,5)),
|
||||
# Else connect TX to encoder
|
||||
).Else(
|
||||
encoder.k[0].eq(k[0]),
|
||||
encoder.k[1].eq(k[1]),
|
||||
encoder.k[2].eq(k[2]),
|
||||
encoder.k[3].eq(k[3]),
|
||||
encoder.d[0].eq(d[0:8]),
|
||||
encoder.d[1].eq(d[8:16]),
|
||||
encoder.d[2].eq(d[16:24]),
|
||||
encoder.d[3].eq(d[24:32])
|
||||
)
|
||||
sink.connect(datapath.sink),
|
||||
datapath.source.ack.eq(1),
|
||||
datapath.idle.eq(idle),
|
||||
datapath.comma.eq(comma)
|
||||
]
|
||||
|
||||
# Data output (DDR with sys4x)
|
||||
# Output Data(DDR with sys4x)
|
||||
data = Signal()
|
||||
self.specials += [
|
||||
Instance("OSERDESE2",
|
||||
|
|
@ -106,10 +78,10 @@ class _S7SerdesTX(Module):
|
|||
i_OCE=1,
|
||||
i_RST=ResetSignal("sys"),
|
||||
i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal("sys"),
|
||||
i_D1=converter.source.data[0], i_D2=converter.source.data[1],
|
||||
i_D3=converter.source.data[2], i_D4=converter.source.data[3],
|
||||
i_D5=converter.source.data[4], i_D6=converter.source.data[5],
|
||||
i_D7=converter.source.data[6], i_D8=converter.source.data[7]
|
||||
i_D1=datapath.source.data[0], i_D2=datapath.source.data[1],
|
||||
i_D3=datapath.source.data[2], i_D4=datapath.source.data[3],
|
||||
i_D5=datapath.source.data[4], i_D6=datapath.source.data[5],
|
||||
i_D7=datapath.source.data[6], i_D8=datapath.source.data[7]
|
||||
),
|
||||
DifferentialOutput(data, pads.tx_p, pads.tx_n)
|
||||
]
|
||||
|
|
@ -127,9 +99,7 @@ class _S7SerdesRX(Module):
|
|||
self.comma = comma = Signal()
|
||||
|
||||
# Datapath
|
||||
self.ce = ce = Signal()
|
||||
self.k = k = Signal(4)
|
||||
self.d = d = Signal(32)
|
||||
self.source = source = stream.Endpoint([("data", 32)])
|
||||
|
||||
# # #
|
||||
|
||||
|
|
@ -170,50 +140,15 @@ class _S7SerdesRX(Module):
|
|||
)
|
||||
]
|
||||
|
||||
# 8 --> 40 converter and bitslip
|
||||
converter = stream.Converter(8, 40)
|
||||
self.submodules += converter
|
||||
bitslip = CEInserter()(BitSlip(40))
|
||||
self.submodules += bitslip
|
||||
# Datapath
|
||||
self.submodules.datapath = datapath = RXDatapath(8)
|
||||
self.comb += [
|
||||
converter.sink.stb.eq(1),
|
||||
converter.source.ack.eq(1),
|
||||
# Enable pipeline when converter outputs the 40 bits
|
||||
ce.eq(converter.source.stb),
|
||||
# Connect input data to converter
|
||||
converter.sink.data.eq(data_deserialized),
|
||||
# Connect converter to bitslip
|
||||
bitslip.ce.eq(ce),
|
||||
bitslip.value.eq(bitslip_value),
|
||||
bitslip.i.eq(converter.source.data)
|
||||
]
|
||||
|
||||
# 8b10b decoder
|
||||
self.submodules.decoders = decoders = [CEInserter()(Decoder(True)) for _ in range(4)]
|
||||
self.comb += [decoders[i].ce.eq(ce) for i in range(4)]
|
||||
self.comb += [
|
||||
# Connect bitslip to decoder
|
||||
decoders[0].input.eq(bitslip.o[0:10]),
|
||||
decoders[1].input.eq(bitslip.o[10:20]),
|
||||
decoders[2].input.eq(bitslip.o[20:30]),
|
||||
decoders[3].input.eq(bitslip.o[30:40]),
|
||||
# Connect decoder to output
|
||||
self.k.eq(Cat(*[decoders[i].k for i in range(4)])),
|
||||
self.d.eq(Cat(*[decoders[i].d for i in range(4)])),
|
||||
]
|
||||
|
||||
# Status
|
||||
idle_timer = WaitTimer(256)
|
||||
self.submodules += idle_timer
|
||||
self.comb += [
|
||||
idle_timer.wait.eq(1),
|
||||
self.idle.eq(idle_timer.done &
|
||||
((bitslip.o == 0) | (bitslip.o == (2**40-1)))),
|
||||
self.comma.eq(
|
||||
(decoders[0].k == 1) & (decoders[0].d == K(28,5)) &
|
||||
(decoders[1].k == 0) & (decoders[1].d == 0) &
|
||||
(decoders[2].k == 0) & (decoders[2].d == 0) &
|
||||
(decoders[3].k == 0) & (decoders[3].d == 0))
|
||||
datapath.sink.stb.eq(1),
|
||||
datapath.sink.data.eq(data_deserialized),
|
||||
datapath.bitslip_value.eq(bitslip_value),
|
||||
datapath.source.connect(source),
|
||||
idle.eq(datapath.idle),
|
||||
comma.eq(datapath.comma)
|
||||
]
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue