From 6fbe0d8ed8c0ce7557a16bf73284d22dd46b1b27 Mon Sep 17 00:00:00 2001
From: Robert Jordens <jordens@gmail.com>
Date: Fri, 23 Feb 2018 13:22:47 +0000
Subject: [PATCH] hmc830: be explicit about SPI mode selection

---
 artiq/firmware/libboard_artiq/hmc830_7043.rs | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs
index dc899ce15..16e9c3e7d 100644
--- a/artiq/firmware/libboard_artiq/hmc830_7043.rs
+++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs
@@ -52,6 +52,8 @@ mod hmc830 {
     fn spi_setup() {
         unsafe {
             while csr::converter_spi::idle_read() == 0 {}
+            // rising egde on CS since cs_polarity still 0
+            // selects "HMC Mode"
             csr::converter_spi::offline_write(0);
             csr::converter_spi::end_write(1);
             csr::converter_spi::cs_polarity_write(0b0001);
@@ -62,30 +64,30 @@ mod hmc830 {
             csr::converter_spi::div_write(16 - 2);
             csr::converter_spi::cs_write(1 << csr::CONFIG_CONVERTER_SPI_HMC830_CS);
 
-            // do a dummy cycle with cs still high to ensure Open mode
-            // (rising CLK before rising CS)
+            // do a dummy cycle with cs still high to clear CS
             csr::converter_spi::length_write(0);
             csr::converter_spi::data_write(0);
             while csr::converter_spi::writable_read() == 0 {}
 
-            csr::converter_spi::length_write(31 - 1);
+            csr::converter_spi::length_write(32 - 1);
         }
     }
 
     fn write(addr: u8, data: u32) {
-        let cmd = (0 << 6) | addr;
-        let val = ((cmd as u32) << 24) | data;
+        let val = ((addr as u32) << 24) | data;
         unsafe {
             while csr::converter_spi::writable_read() == 0 {}
-            csr::converter_spi::data_write(val << 1);
+            csr::converter_spi::data_write(val << 1);  // last clk cycle loads data
             while csr::converter_spi::writable_read() == 0 {}
         }
     }
 
     fn read(addr: u8) -> u32 {
-        write(addr, 0);
+        // SDO (miso/read bits) is technically CPHA=1, while SDI is CPHA=0
+        // trust that the 8.2ns+0.2ns/pF provide enough hold time on top of
+        // the SPI round trip delay and stick with CPHA=0
+        write((1 << 6) | addr, 0);
         unsafe {
-            while csr::converter_spi::writable_read() == 0 {}
             csr::converter_spi::data_read() & 0xffffff
         }
     }