forked from M-Labs/artiq
test: split full_stack into coredevice and coredevice_vs_host
also adapt it to hardware_testbench closes: #62
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parent
4cbf280f1a
commit
6faa8ecd51
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@ -3,6 +3,7 @@ from math import sqrt
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from artiq.language import *
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from artiq.test.hardware_testbench import ExperimentCase
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from artiq.coredevice.runtime_exceptions import RTIOUnderflow
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from artiq.coredevice import runtime_exceptions
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class RTT(Experiment, AutoDB):
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@ -88,6 +89,64 @@ class PulseRate(Experiment, AutoDB):
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break
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class Watchdog(Experiment, AutoDB):
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class DBKeys:
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core = Device()
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@kernel
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def run(self):
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with watchdog(50*ms):
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while True:
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pass
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class LoopbackCount(Experiment, AutoDB):
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class DBKeys:
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core = Device()
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ttl_inout = Device()
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npulses = Argument()
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def report(self, n):
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self.result = n
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@kernel
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def run(self):
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self.ttl_inout.output()
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delay(1*us)
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with parallel:
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self.ttl_inout.gate_rising(10*us)
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with sequential:
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for i in range(self.npulses):
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delay(25*ns)
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self.ttl_inout.pulse(25*ns)
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self.report(self.ttl_inout.count())
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class Underflow(Experiment, AutoDB):
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class DBKeys:
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core = Device()
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ttl_out = Device()
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@kernel
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def run(self):
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while True:
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delay(25*ns)
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self.ttl_out.pulse(25*ns)
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class SequenceError(Experiment, AutoDB):
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class DBKeys:
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core = Device()
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ttl_out = Device()
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@kernel
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def run(self):
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t = now_mu()
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self.ttl_out.pulse(25*us)
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at_mu(t)
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self.ttl_out.pulse(25*us)
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class CoredeviceTest(ExperimentCase):
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def test_rtt(self):
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self.execute(RTT)
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@ -115,6 +174,24 @@ class CoredeviceTest(ExperimentCase):
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self.assertGreater(rate, 100*ns)
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self.assertLess(rate, 2500*ns)
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def test_loopback_count(self):
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npulses = 2
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r = self.execute(LoopbackCount, npulses=npulses)
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self.assertEqual(r.result, npulses)
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def test_underflow(self):
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with self.assertRaises(runtime_exceptions.RTIOUnderflow):
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self.execute(Underflow)
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def test_sequence_error(self):
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with self.assertRaises(runtime_exceptions.RTIOSequenceError):
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self.execute(SequenceError)
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def test_watchdog(self):
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# watchdog only works on the device
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with self.assertRaises(IOError):
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self.execute(Watchdog)
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class RPCTiming(Experiment, AutoDB):
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class DBKeys:
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@ -1,33 +1,19 @@
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import unittest
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from operator import itemgetter
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import os
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from fractions import Fraction
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from artiq import *
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from artiq.coredevice import comm_tcp, core, runtime_exceptions, ttl
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from artiq.sim import devices as sim_devices
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core_device = os.getenv("ARTIQ_CORE_DEVICE")
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def _run_on_device(k_class, **parameters):
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comm = comm_tcp.Comm(host=core_device)
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try:
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coredev = core.Core(comm=comm)
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k_inst = k_class(core=coredev, **parameters)
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k_inst.run()
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finally:
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comm.close()
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from artiq.test.hardware_testbench import ExperimentCase
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def _run_on_host(k_class, **parameters):
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coredev = sim_devices.Core()
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k_inst = k_class(core=coredev, **parameters)
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k_inst.run()
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return k_inst
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class _Primes(AutoDB):
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class _Primes(Experiment, AutoDB):
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class DBKeys:
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core = Device()
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output_list = Argument()
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@ -47,7 +33,10 @@ class _Primes(AutoDB):
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self.output_list.append(x)
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class _Misc(AutoDB):
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class _Misc(Experiment, AutoDB):
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class DBKeys:
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core = Device()
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def build(self):
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self.input = 84
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self.al = [1, 2, 3, 4, 5]
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@ -63,7 +52,7 @@ class _Misc(AutoDB):
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self.list_copy_out = self.list_copy_in
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class _PulseLogger(AutoDB):
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class _PulseLogger(Experiment, AutoDB):
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class DBKeys:
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core = Device()
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output_list = Argument()
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@ -90,7 +79,7 @@ class _PulseLogger(AutoDB):
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self.off(now_mu())
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class _Pulses(AutoDB):
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class _Pulses(Experiment, AutoDB):
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class DBKeys:
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core = Device()
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output_list = Argument()
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@ -118,7 +107,7 @@ class _MyException(Exception):
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pass
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class _Exceptions(AutoDB):
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class _Exceptions(Experiment, AutoDB):
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class DBKeys:
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core = Device()
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trace = Argument()
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@ -162,9 +151,10 @@ class _Exceptions(AutoDB):
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self.trace.append(104)
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class _RPCExceptions(AutoDB):
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class _RPCExceptions(Experiment, AutoDB):
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class DBKeys:
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core = Device()
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catch = Argument(False)
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def build(self):
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self.success = False
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@ -172,53 +162,43 @@ class _RPCExceptions(AutoDB):
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def exception_raiser(self):
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raise _MyException
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@kernel
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def run(self):
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if self.catch:
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self.do_catch()
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else:
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self.do_not_catch()
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@kernel
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def do_not_catch(self):
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self.exception_raiser()
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@kernel
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def catch(self):
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def do_catch(self):
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try:
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self.exception_raiser()
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except _MyException:
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self.success = True
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class _Watchdog(AutoDB):
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class DBKeys:
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core = Device()
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@kernel
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def run(self):
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with watchdog(50*ms):
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while True:
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pass
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@unittest.skipUnless(core_device, "no hardware")
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class ExecutionCase(unittest.TestCase):
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class HostVsDeviceCase(ExperimentCase):
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def test_primes(self):
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l_device, l_host = [], []
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_run_on_device(_Primes, maximum=100, output_list=l_device)
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self.execute(_Primes, maximum=100, output_list=l_device)
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_run_on_host(_Primes, maximum=100, output_list=l_host)
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self.assertEqual(l_device, l_host)
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def test_misc(self):
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comm = comm_tcp.Comm(host=core_device)
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try:
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coredev = core.Core(comm=comm)
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uut = _Misc(core=coredev)
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uut.run()
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for f in self.execute, _run_on_host:
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uut = f(_Misc)
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self.assertEqual(uut.half_input, 42)
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self.assertEqual(uut.decimal_fraction, Fraction("1.2"))
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self.assertEqual(uut.acc, sum(uut.al))
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self.assertEqual(uut.list_copy_in, uut.list_copy_out)
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finally:
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comm.close()
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def test_pulses(self):
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l_device, l_host = [], []
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_run_on_device(_Pulses, output_list=l_device)
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self.execute(_Pulses, output_list=l_device)
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_run_on_host(_Pulses, output_list=l_host)
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l_host = sorted(l_host, key=itemgetter(1))
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for channel in "a", "b", "c", "d":
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@ -229,115 +209,14 @@ class ExecutionCase(unittest.TestCase):
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def test_exceptions(self):
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t_device, t_host = [], []
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with self.assertRaises(IndexError):
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_run_on_device(_Exceptions, trace=t_device)
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self.execute(_Exceptions, trace=t_device)
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with self.assertRaises(IndexError):
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_run_on_host(_Exceptions, trace=t_host)
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self.assertEqual(t_device, t_host)
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def test_rpc_exceptions(self):
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comm = comm_tcp.Comm(host=core_device)
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try:
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uut = _RPCExceptions(core=core.Core(comm=comm))
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for f in self.execute, _run_on_host:
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with self.assertRaises(_MyException):
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uut.do_not_catch()
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uut.catch()
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f(_RPCExceptions, catch=False)
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uut = self.execute(_RPCExceptions, catch=True)
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self.assertTrue(uut.success)
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finally:
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comm.close()
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def test_watchdog(self):
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with self.assertRaises(IOError):
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_run_on_device(_Watchdog)
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class _RTIOLoopback(AutoDB):
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class DBKeys:
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core = Device()
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io = Device()
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npulses = Argument()
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def report(self, n):
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self.result = n
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@kernel
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def run(self):
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self.io.output()
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delay(1*us)
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with parallel:
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self.io.gate_rising(10*us)
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with sequential:
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for i in range(self.npulses):
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delay(25*ns)
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self.io.pulse(25*ns)
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self.report(self.io.count())
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class _RTIOUnderflow(AutoDB):
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class DBKeys:
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core = Device()
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o = Device()
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@kernel
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def run(self):
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while True:
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delay(25*ns)
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self.o.pulse(25*ns)
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class _RTIOSequenceError(AutoDB):
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class DBKeys:
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core = Device()
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o = Device()
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@kernel
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def run(self):
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t = now_mu()
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self.o.pulse(25*us)
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at_mu(t)
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self.o.pulse(25*us)
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@unittest.skipUnless(core_device, "no hardware")
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class RTIOCase(unittest.TestCase):
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# Connect channels 0 and 1 together for this test
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# (C11 and C13 on Papilio Pro)
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def test_loopback(self):
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npulses = 4
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comm = comm_tcp.Comm(host=core_device)
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try:
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coredev = core.Core(comm=comm)
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uut = _RTIOLoopback(
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core=coredev,
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io=ttl.TTLInOut(core=coredev, channel=0),
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npulses=npulses
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)
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uut.run()
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self.assertEqual(uut.result, npulses)
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finally:
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comm.close()
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def test_underflow(self):
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comm = comm_tcp.Comm(host=core_device)
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try:
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coredev = core.Core(comm=comm)
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uut = _RTIOUnderflow(
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core=coredev,
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o=ttl.TTLOut(core=coredev, channel=2)
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)
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with self.assertRaises(runtime_exceptions.RTIOUnderflow):
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uut.run()
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finally:
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comm.close()
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def test_sequence_error(self):
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comm = comm_tcp.Comm(host=core_device)
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try:
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coredev = core.Core(comm=comm)
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uut = _RTIOSequenceError(
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core=coredev,
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o=ttl.TTLOut(core=coredev, channel=2)
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)
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with self.assertRaises(runtime_exceptions.RTIOSequenceError):
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uut.run()
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finally:
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comm.close()
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