coredevice/mirny: support human readable clk_sel

In init(), read hw_rev to derive clk_sel code from user string.

Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>

RELEASE_NOTES.rst

@@ -32,6 +32,8 @@ Highlights:
 * Zotino now exposes  ``voltage_to_mu()``
 * ``ad9910``: The maximum amplitude scale factor is now ``0x3fff`` (was ``0x3ffe``
   before).
+* Mirny now supports HW revision independent, human readable ``clk_sel`` parameters:
+  "XO", "SMA", and "MMCX". Passing an integer is backwards compatible.
 * Dashboard:
    - Applets now restart if they are running and a ccb call changes their spec
    - A "Quick Open" dialog to open experiments by typing part of their name can

artiq/coredevice/mirny.py

@@ -28,6 +28,9 @@ SPI_CS = 1
 
 WE = 1 << 24
 
+# supported CPLD code version
+PROTO_REV_MATCH = 0x0
+
 
 class Mirny:
     """
@@ -37,22 +40,39 @@ class Mirny:
     :param refclk: Reference clock (SMA, MMCX or on-board 100 MHz oscillator)
         frequency in Hz
     :param clk_sel: Reference clock selection.
-        valid options are: 0 - internal 100MHz XO; 1 - front-panel SMA; 2 -
-        internal MMCX
+        valid options are: "XO" - onboard crystal oscillator
+                           "SMA" - front-panel SMA connector
+                           "MMCX" - internal MMCX connector
+        Passing an integer writes its two least significant bits as ``clk_sel``
+        in the CPLD's register 1. The effect depends on the hardware revision.
     :param core_device: Core device name (default: "core")
     """
 
-    kernel_invariants = {"bus", "core"}
+    kernel_invariants = {"bus", "core", "refclk", "clk_sel_hw_rev"}
 
     def __init__(self, dmgr, spi_device, refclk=100e6, clk_sel=0, core_device="core"):
         self.core = dmgr.get(core_device)
         self.bus = dmgr.get(spi_device)
 
+        # reference clock frequency
         self.refclk = refclk
         assert 10 <= self.refclk / 1e6 <= 600, "Invalid refclk"
 
-        self.clk_sel = clk_sel & 0b11
-        assert 0 <= self.clk_sel <= 3, "Invalid clk_sel"
+        # reference clock selection
+        if isinstance(clk_sel, str):
+            self.clk_sel_hw_rev = {
+                # clk source: [v1.1, v1.0]
+                "xo": [0, 0],
+                "mmcx": [3, 2],
+                "sma": [2, 3],
+            }[clk_sel.lower()]
+        else:
+            clk_sel = int(clk_sel) & 0x3
+            self.clk_sel_hw_rev = [clk_sel] * 2
+        self.clk_sel = -1
+
+        # board hardware revision
+        self.hw_rev = 0  # v1.0: 0b11, v1.1: 0b10
 
         # TODO: support clk_div on v1.0 boards
 
@@ -78,15 +98,16 @@ class Mirny:
 
         :param blind: Do not attempt to verify presence and compatibility.
         """
-        if not blind:
         reg0 = self.read_reg(0)
-            if reg0 & 0b11 != 0b11:
-                raise ValueError("Mirny HW_REV mismatch")
-            if (reg0 >> 2) & 0b11 != 0b00:
+        self.hw_rev = reg0 & 0x3
+
+        if not blind:
+            if (reg0 >> 2) & 0x3 != PROTO_REV_MATCH:
                 raise ValueError("Mirny PROTO_REV mismatch")
             delay(100 * us)  # slack
 
         # select clock source
+        self.clk_sel = self.clk_sel_hw_rev[self.hw_rev - 2]
         self.write_reg(1, (self.clk_sel << 4))
         delay(1000 * us)