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sawg: merge set/set64

This commit is contained in:
Robert Jördens 2016-12-01 16:25:01 +01:00
parent 93a853a0e0
commit 6e9bc7c05d
2 changed files with 13 additions and 19 deletions
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13
artiq/coredevice/sawg.py
View File

@ -36,23 +36,18 @@ class Spline:
"""
rtio_output(now_mu(), self.channel, 0, value)
@kernel
@kernel(flags={"fast-math"})
def set(self, value: TFloat):
"""Set spline value.
:param value: Spline value relative to full-scale.
"""
rtio_output(now_mu(), self.channel, 0, self.to_mu(value))
@kernel(flags={"fast-math"})
def set64(self, value: TFloat):
"""Set spline value.
:param value: Spline value relative to full-scale.
"""
if self.width > 32:
l = [int32(0)] * 2
self.pack_coeff_mu([self.to_mu64(value)], l)
rtio_output_wide(now_mu(), self.channel, 0, l)
else:
rtio_output(now_mu(), self.channel, 0, self.to_mu(value))
@kernel
def set_coeff_mu(self, value): # TList(TInt32)

13
artiq/test/gateware/test_sawg_fe.py
View File

@ -55,8 +55,8 @@ class SAWGTest(unittest.TestCase):
d = self.driver
d.offset.set(.9)
delay(2*self.t)
d.frequency0.set64(.1)
d.frequency1.set64(.1)
d.frequency0.set(.1)
d.frequency1.set(.1)
delay(2*self.t)
d.offset.set(0)
v = int(round((1 << 48) * .1 * self.t))
@ -64,10 +64,9 @@ class SAWGTest(unittest.TestCase):
self.rtio_manager.outputs, [
(0., 1, 0, int(round(
(1 << self.driver.offset.width - 1)*.9))),
(2.*self.t, 8, 0, [int(round(
(2.*self.t, 8, 0, int(round(
(1 << self.driver.frequency0.width) *
self.t/self.channel.parallelism*.1)),
0]),
self.t/self.channel.parallelism*.1))),
(2.*self.t, 3, 0, [int32(v), int32(v >> 32)]),
(4.*self.t, 1, 0, 0),
])
@ -200,9 +199,9 @@ class SAWGTest(unittest.TestCase):
self.sawg0.frequency0.set(10*MHz)
self.sawg0.phase0.set(0.)
self.sawg0.frequency1.set64(1*MHz)
self.sawg0.frequency1.set(1*MHz)
self.sawg0.phase1.set(0.)
self.sawg0.frequency2.set64(13*MHz)
self.sawg0.frequency2.set(13*MHz)
self.sawg0.phase2.set(0.)
t = now_mu()
self.sawg0.amplitude1.smooth(.0, a1, t_up, order)