coredevice.ttl: add missed int64 conversion.

2016-03-04 08:37:38 +00:00 · 2016-03-04 08:37:38 +00:00 · 6e44c5424d
parent 7ff0c89d51
commit 6e44c5424d
1 changed files with 1 additions and 1 deletions
--- a/artiq/coredevice/ttl.py
+++ b/artiq/coredevice/ttl.py
@ -238,7 +238,7 @@ class TTLClockGen:

        # in RTIO cycles
        self.previous_timestamp = int(0, width=64)
-        self.acc_width = 24
+        self.acc_width = int(24, width=64)

    @portable
    def frequency_to_ftw(self, frequency):