From 6e43c411038c01ec6d3423db481790861d70e47c Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sat, 5 Jan 2019 23:41:30 +0800
Subject: [PATCH] firmware: support building without SDRAM

---
 artiq/firmware/libboard_misoc/lib.rs        | 2 ++
 artiq/firmware/libboard_misoc/or1k/cache.rs | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/artiq/firmware/libboard_misoc/lib.rs b/artiq/firmware/libboard_misoc/lib.rs
index ad941f00a..1b1b597d9 100644
--- a/artiq/firmware/libboard_misoc/lib.rs
+++ b/artiq/firmware/libboard_misoc/lib.rs
@@ -15,7 +15,9 @@ pub use arch::*;
 
 include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs"));
 include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/csr.rs"));
+#[cfg(has_dfii)]
 include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/sdram_phy.rs"));
+#[cfg(has_dfii)]
 pub mod sdram;
 pub mod ident;
 pub mod clock;
diff --git a/artiq/firmware/libboard_misoc/or1k/cache.rs b/artiq/firmware/libboard_misoc/or1k/cache.rs
index 8e79b11ec..9357917c9 100644
--- a/artiq/firmware/libboard_misoc/or1k/cache.rs
+++ b/artiq/firmware/libboard_misoc/or1k/cache.rs
@@ -1,6 +1,9 @@
+#[cfg(has_ddrphy)]
 use core::ptr;
 use super::spr::*;
+#[cfg(has_ddrphy)]
 use csr;
+#[cfg(has_ddrphy)]
 use mem;
 
 pub fn flush_cpu_icache() {
@@ -35,6 +38,7 @@ pub fn flush_cpu_dcache() {
     }
 }
 
+#[cfg(has_ddrphy)]
 pub fn flush_l2_cache() {
     unsafe {
         for i in 0..2 * (csr::CONFIG_L2_SIZE as usize) / 4 {