From 6df4ae934f07e57f6e61be1bafacf91179b40b01 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Tue, 11 Dec 2018 10:34:01 +0000 Subject: [PATCH] eem: name the servo submodule MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows the migen namer to derive names for the ADC return clock domain in the case of multiple SUServos close #1201 Signed-off-by: Robert Jördens --- artiq/gateware/eem.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/artiq/gateware/eem.py b/artiq/gateware/eem.py index 56f9cb25e..a63d82005 100644 --- a/artiq/gateware/eem.py +++ b/artiq/gateware/eem.py @@ -493,6 +493,7 @@ class SUServo(_EEM): sampler_pads = servo_pads.SamplerPads(target.platform, eem_sampler) urukul_pads = servo_pads.UrukulPads( target.platform, eem_urukul0, eem_urukul1) + target.submodules += sampler_pads, urukul_pads # timings in units of RTIO coarse period adc_p = servo.ADCParams(width=16, channels=8, lanes=4, t_cnvh=4, # account for SCK DDR to CONV latency @@ -505,7 +506,9 @@ class SUServo(_EEM): channels=adc_p.channels, clk=clk) su = servo.Servo(sampler_pads, urukul_pads, adc_p, iir_p, dds_p) su = ClockDomainsRenamer("rio_phy")(su) - target.submodules += sampler_pads, urukul_pads, su + # explicitly name the servo submodule to enable the migen namer to derive + # a name for the adc return clock domain + setattr(target.submodules, "suservo_eem{}".format(eems_sampler[0]), su) ctrls = [rtservo.RTServoCtrl(ctrl) for ctrl in su.iir.ctrl] target.submodules += ctrls