forked from M-Labs/artiq
doc/manual: minor fixes
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@ -1,6 +1,8 @@
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Core language reference
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=======================
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The most commonly used features from those modules can be imported with ``from artiq import *``.
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:mod:`artiq.language.core` module
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---------------------------------
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@ -8,7 +10,7 @@ Core language reference
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:members:
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:mod:`artiq.language.context` module
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---------------------------------
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------------------------------------
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.. automodule:: artiq.language.context
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:members:
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@ -8,11 +8,11 @@ These steps are required to generate bitstream (``.bit``) files, build the MiSoC
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* Install the FPGA vendor tools (e.g. Xilinx ISE and/or Vivado):
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Get Xilinx tools from http://www.xilinx.com/support/download/index.htm. ISE can build bitstreams both for boards using the Spartan-6 (Papilio Pro) and 7-series devices (KC705), while Vivado supports only boards using 7-series devices.
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* Get Xilinx tools from http://www.xilinx.com/support/download/index.htm. ISE can build bitstreams both for boards using the Spartan-6 (Papilio Pro) and 7-series devices (KC705), while Vivado supports only boards using 7-series devices.
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The Papilio Pro is supported by Webpack, the KC705 is not.
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* The Papilio Pro is supported by Webpack, the KC705 is not.
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During the Xilinx toolchain installation, uncheck ``Install cable drivers`` (they are not required as we use better and open source alternatives).
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* During the Xilinx toolchain installation, uncheck ``Install cable drivers`` (they are not required as we use better and open source alternatives).
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* Create a development directory: ::
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