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rtio: add explanation about cri.counter

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Sebastien Bourdeauducq 2017-09-19 12:05:12 +08:00
parent 81d6317053
commit 6dc9cad2c9
1 changed files with 3 additions and 0 deletions
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3
artiq/gateware/rtio/cri.py
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@ -35,6 +35,9 @@ layout = [
# <0> and <1> are mutually exclusive. <1> has higher priority. # <0> and <1> are mutually exclusive. <1> has higher priority.
("i_status", 3, DIR_S_TO_M), ("i_status", 3, DIR_S_TO_M),
# value of the timestamp counter transferred into the CRI clock domain.
# monotonic, may lag behind the counter in the IO clock domain, but
# not be ahead of it.
("counter", 64, DIR_S_TO_M) ("counter", 64, DIR_S_TO_M)
] ]