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rtio: support single-master CRI arbiter

This commit is contained in:
Sebastien Bourdeauducq 2016-12-01 16:30:11 +08:00
parent a318243083
commit 6c97a97d8c
1 changed files with 24 additions and 21 deletions
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3
artiq/gateware/rtio/cri.py
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@ -160,6 +160,9 @@ class CRIArbiter(Module):
# # # # # #
if len(masters) == 1:
self.comb += masters[0].connect(slave)
else:
selected = Signal(max=len(masters)) selected = Signal(max=len(masters))
# mux master->slave signals # mux master->slave signals