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gateware: reverse SDRAM words in RTIO DMA engine.

This commit is contained in:
whitequark 2017-03-17 07:23:45 +00:00
parent 4b14887ddb
commit 6b63322106
2 changed files with 13 additions and 3 deletions
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6
artiq/gateware/rtio/dma.py
View File

@ -7,6 +7,10 @@ from misoc.interconnect import stream, wishbone
from artiq.gateware.rtio import cri from artiq.gateware.rtio import cri
def _reverse_signal(s):
return Cat(s[i] for i in reversed(range(len(s))))
class WishboneReader(Module): class WishboneReader(Module):
def __init__(self, bus=None): def __init__(self, bus=None):
if bus is None: if bus is None:
@ -35,7 +39,7 @@ class WishboneReader(Module):
If(self.source.ack, data_reg_loaded.eq(0)), If(self.source.ack, data_reg_loaded.eq(0)),
If(bus.ack, If(bus.ack,
data_reg_loaded.eq(1), data_reg_loaded.eq(1),
self.source.data.eq(bus.dat_r), self.source.data.eq(_reverse_signal(bus.dat_r)),
self.source.eop.eq(self.sink.eop) self.source.eop.eq(self.sink.eop)
) )
] ]

10
artiq/gateware/test/rtio/test_dma.py
View File

@ -23,7 +23,7 @@ def encode_record(channel, timestamp, address, data):
r += encode_n(channel, 3, 3) r += encode_n(channel, 3, 3)
r += encode_n(timestamp, 8, 8) r += encode_n(timestamp, 8, 8)
r += encode_n(address, 2, 2) r += encode_n(address, 2, 2)
r += encode_n(data, 1, 64) r += encode_n(data, 4, 64)
return encode_n(len(r)+1, 1, 1) + r return encode_n(len(r)+1, 1, 1) + r
@ -33,7 +33,12 @@ def pack(x, size):
n = 0 n = 0
for j, w in enumerate(x[i*size:(i+1)*size]): for j, w in enumerate(x[i*size:(i+1)*size]):
n |= w << j*8 n |= w << j*8
r.append(n) nr = 0
for i in range(size*8):
if (n >> i) & 1: nr |= 1 << (size*8 - 1 - i)
# print("{:064x}".format(n))
# print("{:064x}".format(nr))
r.append(nr)
return r return r
@ -48,6 +53,7 @@ class TB(Module):
def __init__(self, ws): def __init__(self, ws):
sequence = [b for write in test_writes for b in encode_record(*write)] sequence = [b for write in test_writes for b in encode_record(*write)]
sequence.append(0) sequence.append(0)
# print(sequence)
sequence = pack(sequence, ws) sequence = pack(sequence, ws)
bus = wishbone.Interface(ws*8) bus = wishbone.Interface(ws*8)