forked from M-Labs/artiq
firmware/ad9154: use fixed hmc7043 sysref phase (found with scan)
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@ -608,7 +608,8 @@ fn dac_cfg_retry(dacno: u8) -> Result<(), &'static str> {
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dac_cfg(dacno)
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dac_cfg(dacno)
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}
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}
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fn dac_sysref_cfg(dacno: u8) {
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#[allow(dead_code)]
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fn dac_sysref_scan(dacno: u8) {
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let mut sync_error_last = 0u16;
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let mut sync_error_last = 0u16;
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let mut phase_min_found = false;
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let mut phase_min_found = false;
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let mut phase_min = 0u16;
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let mut phase_min = 0u16;
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@ -646,6 +647,11 @@ fn dac_sysref_cfg(dacno: u8) {
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hmc7043::cfg_dac_sysref(dacno, phase_opt);
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hmc7043::cfg_dac_sysref(dacno, phase_opt);
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}
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}
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fn dac_sysref_cfg(dacno: u8, phase: u16) {
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info!("AD9154-{} setting SYSREF phase to {}", dacno, phase);
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hmc7043::cfg_dac_sysref(dacno, phase);
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}
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pub fn init() -> Result<(), &'static str> {
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pub fn init() -> Result<(), &'static str> {
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// Release the JESD clock domain reset late, as we need to
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// Release the JESD clock domain reset late, as we need to
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// set up clock chips before.
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// set up clock chips before.
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@ -654,9 +660,9 @@ pub fn init() -> Result<(), &'static str> {
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for dacno in 0..csr::AD9154.len() {
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for dacno in 0..csr::AD9154.len() {
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let dacno = dacno as u8;
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let dacno = dacno as u8;
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debug!("setting up AD9154-{} DAC...", dacno);
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debug!("setting up AD9154-{} DAC...", dacno);
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dac_sysref_cfg(dacno, 88);
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dac_cfg_retry(dacno)?;
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dac_cfg_retry(dacno)?;
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dac_prbs(dacno)?;
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dac_prbs(dacno)?;
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dac_sysref_cfg(dacno);
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dac_cfg_retry(dacno)?;
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dac_cfg_retry(dacno)?;
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}
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}
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