forked from M-Labs/artiq
drtio: fix link error generation
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parent
d747d74cb3
commit
6aaa8bf9d9
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@ -63,11 +63,6 @@ class RTController(Module):
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self.comb += self.cd_rtio_with_rst.clk.eq(ClockSignal("rtio"))
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self.comb += self.cd_rtio_with_rst.clk.eq(ClockSignal("rtio"))
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self.specials += AsyncResetSynchronizer(self.cd_rtio_with_rst, local_reset)
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self.specials += AsyncResetSynchronizer(self.cd_rtio_with_rst, local_reset)
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self.comb += [
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self.cri.o_status[2].eq(~self.csrs.link_up.storage),
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self.cri.i_status[3].eq(~self.csrs.link_up.storage)
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]
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# protocol errors
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# protocol errors
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err_unknown_packet_type = Signal()
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err_unknown_packet_type = Signal()
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err_packet_truncated = Signal()
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err_packet_truncated = Signal()
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@ -126,7 +121,7 @@ class RTController(Module):
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o_status_underflow = Signal()
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o_status_underflow = Signal()
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self.comb += [
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self.comb += [
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self.cri.o_status.eq(Cat(
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self.cri.o_status.eq(Cat(
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o_status_wait, o_status_underflow)),
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o_status_wait, o_status_underflow, ~self.csrs.link_up.storage)),
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self.csrs.o_wait.status.eq(o_status_wait)
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self.csrs.o_wait.status.eq(o_status_wait)
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]
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]
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o_underflow_set = Signal()
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o_underflow_set = Signal()
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@ -151,7 +146,8 @@ class RTController(Module):
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i_status_overflow = Signal()
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i_status_overflow = Signal()
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i_status_wait_status = Signal()
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i_status_wait_status = Signal()
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self.comb += self.cri.i_status.eq(Cat(
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self.comb += self.cri.i_status.eq(Cat(
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i_status_wait_event, i_status_overflow, i_status_wait_status))
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i_status_wait_event, i_status_overflow, i_status_wait_status,
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~self.csrs.link_up.storage))
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load_read_reply = Signal()
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load_read_reply = Signal()
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self.sync.sys_with_rst += [
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self.sync.sys_with_rst += [
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