forked from M-Labs/artiq
runtime: clear all DRTIO FIFOs first, reset remote PHYs on link init
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8f747fa209
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@ -53,6 +53,13 @@ mod drtio {
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}
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}
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fn reset_phy() {
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unsafe {
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csr::drtio::reset_phy_write(1);
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while csr::drtio::o_wait_read() == 1 {}
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}
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}
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fn sync_tsc() {
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unsafe {
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csr::drtio::set_time_write(1);
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@ -94,9 +101,9 @@ mod drtio {
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waiter.sleep(600).unwrap();
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info!("wait for remote side done");
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init(); // clear all FIFOs first
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reset_phy();
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sync_tsc();
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info!("TSC synced");
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init();
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info!("link initialization completed");
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waiter.until(|| !link_is_up()).unwrap();
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