From 68d16fc292064580a283a4af17c9dfe2391aa781 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 13 Jun 2018 21:28:15 +0800 Subject: [PATCH] serwb: support single-ended signals Low-speed PHY only. --- artiq/gateware/serwb/genphy.py | 22 ++++++++++++++++++---- artiq/gateware/targets/sayma_rtm.py | 2 +- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/artiq/gateware/serwb/genphy.py b/artiq/gateware/serwb/genphy.py index b9d6c02f2..d4d5c0cc5 100644 --- a/artiq/gateware/serwb/genphy.py +++ b/artiq/gateware/serwb/genphy.py @@ -18,10 +18,18 @@ class _SerdesClocking(Module): # can use this clock to sample data if mode == "master": self.specials += DDROutput(0, 1, self.refclk) - self.specials += DifferentialOutput(self.refclk, pads.clk_p, pads.clk_n) + if hasattr(pads, "clk_p"): + self.specials += DifferentialOutput(self.refclk, pads.clk_p, pads.clk_n) + else: + self.comb += pads.clk.eq(self.refclk) # In Slave mode, use the clock provided by Master elif mode == "slave": - self.specials += DifferentialInput(pads.clk_p, pads.clk_n, self.refclk) + if hasattr(pads, "clk_p"): + self.specials += DifferentialInput(pads.clk_p, pads.clk_n, self.refclk) + else: + self.comb += self.refclk.eq(pads.clk) + else: + raise ValueError class _SerdesTX(Module): @@ -47,7 +55,10 @@ class _SerdesTX(Module): # Output data (on rising edge of sys_clk) data = Signal() self.sync += data.eq(datapath.source.data) - self.specials += DifferentialOutput(data, pads.tx_p, pads.tx_n) + if hasattr(pads, "tx_p"): + self.specials += DifferentialOutput(data, pads.tx_p, pads.tx_n) + else: + self.comb += pads.tx.eq(data) class _SerdesRX(Module): @@ -67,7 +78,10 @@ class _SerdesRX(Module): # Input data (on rising edge of sys_clk) data = Signal() data_d = Signal() - self.specials += DifferentialInput(pads.rx_p, pads.rx_n, data) + if hasattr(pads, "rx_p"): + self.specials += DifferentialInput(pads.rx_p, pads.rx_n, data) + else: + self.comb += data.eq(pads.rx) self.sync += data_d.eq(data) # Datapath diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index e3fca7e3e..ed440f891 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -183,7 +183,7 @@ class SaymaRTM(Module): # AMC/RTM serwb serwb_pads = platform.request("amc_rtm_serwb") - platform.add_period_constraint(serwb_pads.clk_p, 8.) + platform.add_period_constraint(serwb_pads.clk, 8.) serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="slave") self.submodules.serwb_phy_rtm = serwb_phy_rtm self.comb += [