forked from M-Labs/artiq
gateware: extend mailbox to 3 entries.
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parent
6aa13fbf25
commit
6872017449
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@ -3,19 +3,19 @@ from misoc.interconnect import wishbone
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class Mailbox(Module):
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class Mailbox(Module):
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def __init__(self):
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def __init__(self, size=1):
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self.i1 = wishbone.Interface()
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self.i1 = wishbone.Interface()
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self.i2 = wishbone.Interface()
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self.i2 = wishbone.Interface()
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# # #
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# # #
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value = Signal(32)
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values = Array([Signal(32) for _ in range(size)])
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for i in self.i1, self.i2:
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for i in self.i1, self.i2:
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self.sync += [
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self.sync += [
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i.dat_r.eq(value),
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i.dat_r.eq(values[i.adr]),
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i.ack.eq(0),
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i.ack.eq(0),
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If(i.cyc & i.stb & ~i.ack,
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If(i.cyc & i.stb & ~i.ack,
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i.ack.eq(1),
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i.ack.eq(1),
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If(i.we, value.eq(i.dat_w))
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If(i.we, values[i.adr].eq(i.dat_w))
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)
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)
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]
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]
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@ -28,7 +28,7 @@ class AMPSoC:
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self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)
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self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)
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self.csr_devices.append("kernel_cpu")
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self.csr_devices.append("kernel_cpu")
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self.submodules.mailbox = amp.Mailbox()
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self.submodules.mailbox = amp.Mailbox(size=3)
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self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
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self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
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self.mailbox.i1)
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self.mailbox.i1)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
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