forked from M-Labs/artiq
drtio: RTPacketMaster RX, untested
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3b4a40401a
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@ -506,5 +506,35 @@ class RTPacketMaster(Module):
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)
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# RX FSM
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rx_fsm = ClockDomainsRenamer("rtio_rx")(FSM())
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rx_fsm = ClockDomainsRenamer("rtio_rx")(FSM(reset_state="INPUT"))
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self.submodules += rx_fsm
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echo_reply_now = Signal()
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self.sync.rtio_rx += self.echo_reply_now.eq(echo_reply_now)
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rx_fsm.act("INPUT",
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If(rx_dp.frame_r,
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rx_dp.packet_buffer_load.eq(1),
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If(rx_dp.packet_last,
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Case(rx_dp.packet_type, {
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rx_plm.types["error"]: NextState("ERROR"),
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rx_plm.types["echo_reply"]: echo_reply_now.eq(1),
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rx_plm.types["fifo_level_reply"]: NextState("FIFO_LEVEL"),
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"default": [
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error_not.eq(1),
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error_code.eq(error_codes["unknown_type"])
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]
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})
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)
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)
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)
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rx_fsm.act("ERROR",
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error_not.eq(1),
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error_code.eq(rx_dp.packet_as["error"].code),
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NextState("INPUT")
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)
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rx_fsm.act("FIFO_LEVEL",
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fifo_level_not.eq(1),
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fifo_level.eq(rx_dp.packet_as["fifo_level_reply"].level),
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NextState("INPUT")
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)
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