srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

drtio: RTPacketMaster RX, untested

This commit is contained in:
Sebastien Bourdeauducq 2016-10-22 01:04:14 +08:00
parent 3b4a40401a
commit 67c19ab178
1 changed files with 31 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
artiq/gateware/drtio/rt_packets.py
View File

@ -506,5 +506,35 @@ class RTPacketMaster(Module):
)
# RX FSM
rx_fsm = ClockDomainsRenamer("rtio_rx")(FSM())
rx_fsm = ClockDomainsRenamer("rtio_rx")(FSM(reset_state="INPUT"))
self.submodules += rx_fsm
echo_reply_now = Signal()
self.sync.rtio_rx += self.echo_reply_now.eq(echo_reply_now)
rx_fsm.act("INPUT",
If(rx_dp.frame_r,
rx_dp.packet_buffer_load.eq(1),
If(rx_dp.packet_last,
Case(rx_dp.packet_type, {
rx_plm.types["error"]: NextState("ERROR"),
rx_plm.types["echo_reply"]: echo_reply_now.eq(1),
rx_plm.types["fifo_level_reply"]: NextState("FIFO_LEVEL"),
"default": [
error_not.eq(1),
error_code.eq(error_codes["unknown_type"])
]
})
)
)
)
rx_fsm.act("ERROR",
error_not.eq(1),
error_code.eq(rx_dp.packet_as["error"].code),
NextState("INPUT")
)
rx_fsm.act("FIFO_LEVEL",
fifo_level_not.eq(1),
fifo_level.eq(rx_dp.packet_as["fifo_level_reply"].level),
NextState("INPUT")
)