forked from M-Labs/artiq
urukul: raise instead of assert, clean up
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e3d66d286d
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@ -44,7 +44,7 @@ class AD9910:
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self.cpld = dmgr.get(cpld_device)
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self.core = self.cpld.core
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self.bus = self.cpld.bus
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assert chip_select >= 4
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assert 4 <= chip_select <= 7
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self.chip_select = chip_select
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if sw_device:
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self.sw = dmgr.get(sw_device)
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@ -61,13 +61,12 @@ class AD9910:
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self.pll_cp = pll_cp
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@kernel
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def write(self, addr, data, length=4):
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assert (length == 2) or (length == 4)
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def write32(self, addr, data):
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self.bus.set_xfer(self.chip_select, 8, 0)
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self.bus.write(addr << 24)
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delay_mu(-self.bus.xfer_period_mu)
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self.bus.set_xfer(self.chip_select, length*8, 0)
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self.bus.write(data << (32 - length*8))
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self.bus.set_xfer(self.chip_select, 32, 0)
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self.bus.write(data)
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delay_mu(self.bus.xfer_period_mu - self.bus.write_period_mu)
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@kernel
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@ -82,36 +81,32 @@ class AD9910:
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delay_mu(t - 2*self.bus.write_period_mu)
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@kernel
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def read(self, addr, length=4):
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assert length >= 2
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assert length <= 4
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def read32(self, addr):
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self.bus.set_xfer(self.chip_select, 8, 0)
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self.bus.write((addr | 0x80) << 24)
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delay_mu(-self.bus.xfer_period_mu)
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self.bus.set_xfer(self.chip_select, 0, length*8)
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self.bus.set_xfer(self.chip_select, 0, 32)
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self.bus.write(0)
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delay_mu(2*self.bus.xfer_period_mu)
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data = self.bus.read_sync()
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if length < 4:
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data &= (1 << (length*8)) - 1
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return data
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@kernel
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def init(self):
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# self.cpld.io_rst()
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self.write(_AD9910_REG_CFR1, 0x00000002)
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self.write32(_AD9910_REG_CFR1, 0x00000002)
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delay(100*ns)
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self.cpld.io_update.pulse(100*ns)
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aux_dac = self.read(_AD9910_REG_AUX_DAC)
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assert aux_dac & 0xff == 0x7f
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aux_dac = self.read32(_AD9910_REG_AUX_DAC)
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if aux_dac & 0xff != 0x7f:
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raise ValueError("Urukul AD9910 AUX_DAC mismatch")
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delay(10*us)
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self.write(_AD9910_REG_CFR2, 0x01400020)
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self.write32(_AD9910_REG_CFR2, 0x01400020)
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cfr3 = (0x0807c100 | (self.pll_vco << 24) |
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(self.pll_cp << 19) | (self.pll_n << 1))
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self.write(_AD9910_REG_CFR3, cfr3 | 0x400) # PFD reset
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self.write32(_AD9910_REG_CFR3, cfr3 | 0x400) # PFD reset
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delay(10*us)
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self.cpld.io_update.pulse(100*ns)
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self.write(_AD9910_REG_CFR3, cfr3)
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self.write32(_AD9910_REG_CFR3, cfr3)
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delay(10*us)
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self.cpld.io_update.pulse(100*ns)
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for i in range(100):
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@ -21,7 +21,7 @@ class AD9912:
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self.cpld = dmgr.get(cpld_device)
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self.core = self.cpld.core
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self.bus = self.cpld.bus
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assert chip_select >= 4
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assert 4 <= chip_select <= 7
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self.chip_select = chip_select
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if sw_device:
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self.sw = dmgr.get(sw_device)
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@ -60,7 +60,8 @@ class AD9912:
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t = now_mu()
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self.write(AD9912_SER_CONF, 0x99)
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prodid = self.read(AD9912_PRODIDH, length=2)
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assert (prodid == 0x1982) or (prodid == 0x1902)
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if (prodid != 0x1982) and (prodid != 0x1902):
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raise ValueError("Urukul AD9912 product id mismatch")
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delay(10*us)
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self.write(AD9912_PWRCNTRL1, 0x80) # HSTL, CMOS power down
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delay(10*us)
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@ -1,5 +1,5 @@
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from artiq.language.core import kernel, delay_mu, delay, now_mu, at_mu
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from artiq.language.units import us
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from artiq.language.units import us, ms
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from numpy import int32, int64
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@ -126,8 +126,9 @@ class CPLD:
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io_update=0, mask_nu=0, clk_sel=clk_sel,
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sync_sel=sync_sel, rst=0, io_rst=0)
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self.cfg_write(cfg | (1 << CFG_RST) | (1 << CFG_IO_RST))
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delay(100*us)
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delay(1*ms)
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self.cfg_write(cfg)
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delay(10*ms) # DDS wake up
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proto_rev = urukul_sta_proto_rev(self.sta_read())
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if proto_rev != STA_PROTO_REV_MATCH:
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raise ValueError("Urukul proto_rev mismatch")
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@ -29,7 +29,6 @@ class UrukulTest(EnvExperiment):
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self.led.off()
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self.urukul_cpld.init(clk_sel=1)
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delay(1*ms) # DDS wake up
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self.urukul_ch0b.init()
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self.urukul_ch1b.init()
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self.urukul_ch2b.init()
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