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gateware: add cri_con CSRs to all DMA-capable targets

This commit is contained in:
Sebastien Bourdeauducq 2017-04-06 01:14:01 +08:00
parent 5e3aef45dc
commit 674bf82f3a
3 changed files with 5 additions and 1 deletions
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2
artiq/gateware/targets/kc705_dds.py
View File

@ -100,9 +100,9 @@ _ams101_dac = [
class _NIST_Ions(MiniSoC, AMPSoC): class _NIST_Ions(MiniSoC, AMPSoC):
mem_map = { mem_map = {
"cri_con": 0x10000000,
"rtio": 0x20000000, "rtio": 0x20000000,
"rtio_dma": 0x30000000, "rtio_dma": 0x30000000,
"cri_con": 0x50000000,
"mailbox": 0x70000000 "mailbox": 0x70000000
} }
mem_map.update(MiniSoC.mem_map) mem_map.update(MiniSoC.mem_map)

2
artiq/gateware/targets/kc705_drtio_master.py
View File

@ -21,6 +21,7 @@ from artiq import __version__ as artiq_version
class Master(MiniSoC, AMPSoC): class Master(MiniSoC, AMPSoC):
mem_map = { mem_map = {
"cri_con": 0x10000000,
"rtio": 0x20000000, "rtio": 0x20000000,
"rtio_dma": 0x30000000, "rtio_dma": 0x30000000,
"drtio_aux": 0x50000000, "drtio_aux": 0x50000000,
@ -114,6 +115,7 @@ class Master(MiniSoC, AMPSoC):
self.submodules.cri_con = rtio.CRIInterconnectShared( self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri], [self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri, self.drtio.cri]) [self.rtio_core.cri, self.drtio.cri])
self.register_kernel_cpu_csrdevice("cri_con")
def main(): def main():

2
artiq/gateware/targets/phaser.py
View File

@ -156,6 +156,7 @@ class AD9154(Module, AutoCSR):
class Phaser(MiniSoC, AMPSoC): class Phaser(MiniSoC, AMPSoC):
mem_map = { mem_map = {
"cri_con": 0x10000000,
"rtio": 0x20000000, "rtio": 0x20000000,
# "rtio_dma": 0x30000000, # "rtio_dma": 0x30000000,
"mailbox": 0x70000000, "mailbox": 0x70000000,
@ -240,6 +241,7 @@ class Phaser(MiniSoC, AMPSoC):
self.submodules.cri_con = rtio.CRIInterconnectShared( self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri], # , self.rtio_dma.cri], [self.rtio.cri], # , self.rtio_dma.cri],
[self.rtio_core.cri]) [self.rtio_core.cri])
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj") self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri, self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,