forked from M-Labs/artiq
ddb_template: urukul fixes
* fix/add sw (ad9912 and ad9910) * allow pll_n to be changed
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@ -191,9 +191,9 @@ class PeripheralManager:
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"module": "artiq.coredevice.ad9910",
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"class": "AD9910",
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"arguments": {{
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"pll_n": 32,
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"pll_n": {pll_n},
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"chip_select": {chip_select},
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"cpld_device": "{name}_cpld"{pll_vco}{sync_delay_seed}{io_update_delay}
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"cpld_device": "{name}_cpld"{sw}{pll_vco}{sync_delay_seed}{io_update_delay}
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}}
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}}""",
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name=urukul_name,
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@ -201,6 +201,7 @@ class PeripheralManager:
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uchn=i,
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sw=",\n \"sw_device\": \"ttl_{name}_sw{uchn}\"".format(name=urukul_name, uchn=i) if len(peripheral["ports"]) > 1 else "",
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pll_vco=",\n \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "",
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pll_n=peripheral.get("pll_n", 32),
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sync_delay_seed=",\n \"sync_delay_seed\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "",
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io_update_delay=",\n \"io_update_delay\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "")
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elif dds == "ad9912":
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@ -210,16 +211,17 @@ class PeripheralManager:
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"module": "artiq.coredevice.ad9912",
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"class": "AD9912",
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"arguments": {{
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"pll_n": 8,
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"pll_n": {pll_n},
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"chip_select": {chip_select},
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"cpld_device": "{name}_cpld",
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"sw_device": "ttl_{name}_sw{uchn}"{pll_vco}
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"cpld_device": "{name}_cpld"{sw}{pll_vco}
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}}
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}}""",
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name=urukul_name,
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chip_select=4 + i,
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uchn=i,
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pll_vco=",\n \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "")
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sw=",\n \"sw_device\": \"ttl_{name}_sw{uchn}\"".format(name=urukul_name, uchn=i) if len(peripheral["ports"]) > 1 else "",
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pll_vco=",\n \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "",
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pll_n=peripheral.get("pll_n", 8))
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else:
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raise ValueError
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return next(channel)
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