From 65ec6c28f4ef5c923930b2230d2639d02eaa922f Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sat, 4 Jul 2015 19:21:25 +0200
Subject: [PATCH] ttl/clockgen: expose acc_width

---
 artiq/coredevice/ttl.py | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/artiq/coredevice/ttl.py b/artiq/coredevice/ttl.py
index 768fc161e..431958fb7 100644
--- a/artiq/coredevice/ttl.py
+++ b/artiq/coredevice/ttl.py
@@ -224,20 +224,21 @@ class TTLClockGen(AutoDB):
     def build(self):
         # in RTIO cycles
         self.previous_timestamp = int64(0)
+        self.acc_width = 24
 
     @portable
     def frequency_to_ftw(self, frequency):
         """Returns the frequency tuning word corresponding to the given
         frequency.
         """
-        return round(2**24*frequency*self.core.ref_period)
+        return round(2**self.acc_width*frequency*self.core.ref_period)
 
     @portable
     def ftw_to_frequency(self, ftw):
         """Returns the frequency corresponding to the given frequency tuning
         word.
         """
-        return ftw/self.core.ref_period/2**24
+        return ftw/self.core.ref_period/2**self.acc_width
 
     @kernel
     def set_mu(self, frequency):