forked from M-Labs/artiq
ttl/clockgen: expose acc_width
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@ -224,20 +224,21 @@ class TTLClockGen(AutoDB):
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def build(self):
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# in RTIO cycles
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self.previous_timestamp = int64(0)
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self.acc_width = 24
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@portable
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def frequency_to_ftw(self, frequency):
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"""Returns the frequency tuning word corresponding to the given
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frequency.
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"""
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return round(2**24*frequency*self.core.ref_period)
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return round(2**self.acc_width*frequency*self.core.ref_period)
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@portable
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def ftw_to_frequency(self, ftw):
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"""Returns the frequency corresponding to the given frequency tuning
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word.
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"""
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return ftw/self.core.ref_period/2**24
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return ftw/self.core.ref_period/2**self.acc_width
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@kernel
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def set_mu(self, frequency):
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