forked from M-Labs/artiq
rtio: clean up error-prone rtlink.get_or_zero()
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53860868f4
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65baca8c57
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@ -190,8 +190,10 @@ class Core(Module, AutoCSR):
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self.specials += AsyncResetSynchronizer(self.cd_rio_phy, cmd_reset_phy)
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# TSC
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fine_ts_width = max(rtlink.get_fine_ts_width(channel.interface)
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for channel in channels)
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fine_ts_width = max(max(rtlink.get_fine_ts_width(channel.interface.o)
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for channel in channels),
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max(rtlink.get_fine_ts_width(channel.interface.i)
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for channel in channels))
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coarse_ts = Signal(64-fine_ts_width)
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self.sync.rtio += coarse_ts.eq(coarse_ts + 1)
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coarse_ts_cdc = GrayCodeTransfer(len(coarse_ts))
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@ -69,14 +69,13 @@ class Interface:
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def _get_or_zero(interface, attr):
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if isinstance(interface, Interface):
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return max(_get_or_zero(interface.i, attr),
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_get_or_zero(interface.o, attr))
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if interface is None:
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return 0
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assert isinstance(interface, (OInterface, IInterface))
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if hasattr(interface, attr):
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return len(getattr(interface, attr))
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else:
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if hasattr(interface, attr):
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return len(getattr(interface, attr))
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else:
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return 0
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return 0
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def get_data_width(interface):
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@ -27,7 +27,7 @@ class SED(Module):
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else:
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raise ValueError
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fine_ts_width = max(rtlink.get_fine_ts_width(c.interface)
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fine_ts_width = max(rtlink.get_fine_ts_width(c.interface.o)
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for c in channels)
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seqn_width = layouts.seqn_width(lane_count, fifo_depth)
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@ -4,9 +4,9 @@ from artiq.gateware.rtio import rtlink
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def fifo_payload(channels):
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address_width = max(rtlink.get_address_width(channel.interface)
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address_width = max(rtlink.get_address_width(channel.interface.o)
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for channel in channels)
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data_width = max(rtlink.get_data_width(channel.interface)
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data_width = max(rtlink.get_data_width(channel.interface.o)
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for channel in channels)
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layout = [
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@ -46,11 +46,11 @@ def fifo_egress(seqn_width, layout_payload):
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def output_network_payload(channels):
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fine_ts_width = max(rtlink.get_fine_ts_width(channel.interface)
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fine_ts_width = max(rtlink.get_fine_ts_width(channel.interface.o)
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for channel in channels)
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address_width = max(rtlink.get_address_width(channel.interface)
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address_width = max(rtlink.get_address_width(channel.interface.o)
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for channel in channels)
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data_width = max(rtlink.get_data_width(channel.interface)
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data_width = max(rtlink.get_data_width(channel.interface.o)
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for channel in channels)
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layout = [("channel", bits_for(len(channels)-1))]
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