From 652c2a185f27edbe48b1894ff3494ce0a09ac8c5 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 24 Feb 2016 18:12:12 +0000 Subject: [PATCH] test: rewrite tests using ttl_inout to use loop_{in,out} (#265). --- artiq/test/coredevice/test_analyzer.py | 11 +++---- artiq/test/coredevice/test_rtio.py | 43 +------------------------- examples/master/device_db.pyon | 1 - 3 files changed, 6 insertions(+), 49 deletions(-) diff --git a/artiq/test/coredevice/test_analyzer.py b/artiq/test/coredevice/test_analyzer.py index b607ecc36..f28fa1cda 100644 --- a/artiq/test/coredevice/test_analyzer.py +++ b/artiq/test/coredevice/test_analyzer.py @@ -6,18 +6,17 @@ from artiq.test.hardware_testbench import ExperimentCase class CreateTTLPulse(EnvExperiment): def build(self): self.setattr_device("core") - self.setattr_device("ttl_inout") + self.setattr_device("loop_in") + self.setattr_device("loop_out") @kernel def run(self): - self.ttl_inout.output() - delay_mu(100) with parallel: - self.ttl_inout.gate_both_mu(1200) + self.loop_in.gate_both_mu(1200) with sequential: delay_mu(100) - self.ttl_inout.pulse_mu(1000) - self.ttl_inout.count() + self.loop_out.pulse_mu(1000) + self.loop_in.count() class AnalyzerTest(ExperimentCase): diff --git a/artiq/test/coredevice/test_rtio.py b/artiq/test/coredevice/test_rtio.py index 1bccf6e42..ba05b8f73 100644 --- a/artiq/test/coredevice/test_rtio.py +++ b/artiq/test/coredevice/test_rtio.py @@ -20,7 +20,7 @@ class RTT(EnvExperiment): def run(self): self.ttl_inout.output() delay(1*us) - with parallel: + with interleave: # make sure not to send two commands into the same RTIO # channel with the same timestamp self.ttl_inout.gate_rising(5*us) @@ -101,28 +101,6 @@ class Watchdog(EnvExperiment): pass -class LoopbackCount(EnvExperiment): - def build(self): - self.setattr_device("core") - self.setattr_device("ttl_inout") - self.setattr_argument("npulses") - - def set_count(self, count): - self.set_dataset("count", count) - - @kernel - def run(self): - self.ttl_inout.output() - delay(5*us) - with parallel: - self.ttl_inout.gate_rising(10*us) - with sequential: - for i in range(self.npulses): - delay(25*ns) - self.ttl_inout.pulse(25*ns) - self.set_dataset("count", self.ttl_inout.count()) - - class Underflow(EnvExperiment): def build(self): self.setattr_device("core") @@ -185,17 +163,6 @@ class Handover(EnvExperiment): class CoredeviceTest(ExperimentCase): - @unittest.skipUnless(artiq_low_latency, - "timings are dependent on CPU load and network conditions") - def test_rtt(self): - self.execute(RTT) - rtt = self.dataset_mgr.get("rtt") - print(rtt) - self.assertGreater(rtt, 0*ns) - self.assertLess(rtt, 100*ns) - - @unittest.skipUnless(artiq_low_latency, - "timings are dependent on CPU load and network conditions") def test_loopback(self): self.execute(Loopback) rtt = self.dataset_mgr.get("rtt") @@ -208,8 +175,6 @@ class CoredeviceTest(ExperimentCase): count = self.dataset_mgr.get("count") self.assertEqual(count, 10) - @unittest.skipUnless(artiq_low_latency, - "timings are dependent on CPU load and network conditions") def test_pulse_rate(self): self.execute(PulseRate) rate = self.dataset_mgr.get("pulse_rate") @@ -217,12 +182,6 @@ class CoredeviceTest(ExperimentCase): self.assertGreater(rate, 100*ns) self.assertLess(rate, 2500*ns) - def test_loopback_count(self): - npulses = 2 - self.execute(LoopbackCount, npulses=npulses) - count = self.dataset_mgr.get("count") - self.assertEqual(count, npulses) - def test_underflow(self): with self.assertRaises(RTIOUnderflow): self.execute(Underflow) diff --git a/examples/master/device_db.pyon b/examples/master/device_db.pyon index e2fe7eed1..59b32de2f 100644 --- a/examples/master/device_db.pyon +++ b/examples/master/device_db.pyon @@ -157,7 +157,6 @@ "command": "lda_controller -p {port} --bind {bind} --simulation" }, - "ttl_inout": "pmt0", "ttl_out": "ttl0", "ttl_out_serdes": "ttl0",