srenblad/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

wrpll: remove unnecessary delay

Browse Source 
Counting now happens in the sys domain with no CDC between counter and CPU.
This commit is contained in:
Sebastien Bourdeauducq 2019-12-30 20:01:06 +08:00
parent f57f235dca
commit 642a305c6a
1 changed files with 0 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
artiq/firmware/libboard_artiq/wrpll.rs
View File

@ -269,7 +269,6 @@ fn get_frequencies() -> (u32, u32, u32) {
csr::wrpll::frequency_counter_update_en_write(1); csr::wrpll::frequency_counter_update_en_write(1);
clock::spin_us(200_000); // wait for at least one update clock::spin_us(200_000); // wait for at least one update
csr::wrpll::frequency_counter_update_en_write(0); csr::wrpll::frequency_counter_update_en_write(0);
clock::spin_us(1);
let helper = csr::wrpll::frequency_counter_counter_helper_read(); let helper = csr::wrpll::frequency_counter_counter_helper_read();
let main = csr::wrpll::frequency_counter_counter_rtio_read(); let main = csr::wrpll::frequency_counter_counter_rtio_read();
let cdr = csr::wrpll::frequency_counter_counter_rtio_rx0_read(); let cdr = csr::wrpll::frequency_counter_counter_rtio_rx0_read();