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Commit missing parts of 7f914a0
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@ -191,6 +191,7 @@ class LLVMIRGenerator:
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and len(lltyp.elements) <= 2:
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return not any([self.needs_sret(elt, may_be_large=False) for elt in lltyp.elements])
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else:
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assert isinstance(lltyp, ll.Type)
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return True
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def has_sret(self, functy):
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@ -1239,7 +1240,7 @@ class LLVMIRGenerator:
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return self.llbuilder.ret_void()
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else:
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llvalue = self.map(insn.value())
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if self.needs_sret(llvalue):
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if self.needs_sret(llvalue.type):
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self.llbuilder.store(llvalue, self.llfunction.args[0])
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return self.llbuilder.ret_void()
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else:
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