From 63f1a6d197b823e054c5c58125e94485bfc17e73 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 6 Jan 2023 18:33:13 +0800
Subject: [PATCH] drtio: partially fix tests

---
 artiq/gateware/test/drtio/test_full_stack.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/artiq/gateware/test/drtio/test_full_stack.py b/artiq/gateware/test/drtio/test_full_stack.py
index ade67f5a9..4c7d367b2 100644
--- a/artiq/gateware/test/drtio/test_full_stack.py
+++ b/artiq/gateware/test/drtio/test_full_stack.py
@@ -52,7 +52,7 @@ class DUT(Module):
         self.ttl1 = Signal()
         self.transceivers = DummyTransceiverPair(nwords)
 
-        self.submodules.tsc_master = rtio.TSC("async")
+        self.submodules.tsc_master = rtio.TSC()
         self.submodules.master = DRTIOMaster(self.tsc_master,
                                              self.transceivers.alice)
         self.submodules.master_ki = rtio.KernelInitiator(self.tsc_master,
@@ -144,8 +144,8 @@ class OutputsTestbench:
 
 
 class TestFullStack(unittest.TestCase):
-    clocks = {"sys": 8, "rtio_rx": 5,
-              "rio": 5, "rio_phy": 5}
+    clocks = {"sys": 8, "rtio_rx": 8,
+              "rio": 8, "rio_phy": 8}
 
     def test_pulses(self):
         tb = OutputsTestbench()