forked from M-Labs/artiq
coredevice/cache: port to nac3
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5db9bc9bd4
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6388b82455
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@ -1,23 +1,29 @@
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from artiq.language.core import *
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from numpy import int32
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from artiq.language.types import *
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from artiq.language.core import nac3, extern, kernel, KernelInvariant
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from artiq.coredevice.core import Core
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@syscall(flags={"nounwind"})
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@extern
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def cache_get(key: TStr) -> TList(TInt32):
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def cache_get(key: str) -> list[int32]:
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raise NotImplementedError("syscall not simulated")
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raise NotImplementedError("syscall not simulated")
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@syscall
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@extern
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def cache_put(key: TStr, value: TList(TInt32)) -> TNone:
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def cache_put(key: str, value: list[int32]):
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raise NotImplementedError("syscall not simulated")
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raise NotImplementedError("syscall not simulated")
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@nac3
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class CoreCache:
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class CoreCache:
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"""Core device cache access"""
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"""Core device cache access"""
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core: KernelInvariant[Core]
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def __init__(self, dmgr, core_device="core"):
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def __init__(self, dmgr, core_device="core"):
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self.core = dmgr.get(core_device)
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self.core = dmgr.get(core_device)
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@kernel
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@kernel
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def get(self, key):
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def get(self, key: str) -> list[int32]:
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"""Extract a value from the core device cache.
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"""Extract a value from the core device cache.
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After a value is extracted, it cannot be replaced with another value using
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After a value is extracted, it cannot be replaced with another value using
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:meth:`put` until all kernel functions finish executing; attempting
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:meth:`put` until all kernel functions finish executing; attempting
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@ -34,7 +40,7 @@ class CoreCache:
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return cache_get(key)
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return cache_get(key)
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@kernel
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@kernel
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def put(self, key, value):
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def put(self, key: str, value: list[int32]):
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"""Put a value into the core device cache. The value will persist until reboot.
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"""Put a value into the core device cache. The value will persist until reboot.
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To remove a value from the cache, call :meth:`put` with an empty list.
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To remove a value from the cache, call :meth:`put` with an empty list.
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@ -1,5 +1,6 @@
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from artiq.experiment import *
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from artiq.experiment import *
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from artiq.coredevice.core import Core
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from artiq.coredevice.core import Core
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from artiq.coredevice.cache import CoreCache
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from artiq.coredevice.zotino import Zotino
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from artiq.coredevice.zotino import Zotino
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from artiq.coredevice.mirny import Mirny as MirnyCPLD
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from artiq.coredevice.mirny import Mirny as MirnyCPLD
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from artiq.coredevice.adf5356 import ADF5356
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from artiq.coredevice.adf5356 import ADF5356
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@ -12,6 +13,7 @@ from artiq.coredevice.edge_counter import EdgeCounter
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@nac3
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@nac3
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class NAC3Devices(EnvExperiment):
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class NAC3Devices(EnvExperiment):
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core: KernelInvariant[Core]
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core: KernelInvariant[Core]
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core_cache: KernelInvariant[CoreCache]
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zotino0: KernelInvariant[Zotino]
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zotino0: KernelInvariant[Zotino]
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mirny0_cpld: KernelInvariant[MirnyCPLD]
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mirny0_cpld: KernelInvariant[MirnyCPLD]
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mirny0_ch0: KernelInvariant[ADF5356]
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mirny0_ch0: KernelInvariant[ADF5356]
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@ -22,6 +24,7 @@ class NAC3Devices(EnvExperiment):
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def build(self):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("core")
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self.setattr_device("core_cache")
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self.setattr_device("zotino0")
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self.setattr_device("zotino0")
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self.setattr_device("mirny0_cpld")
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self.setattr_device("mirny0_cpld")
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self.setattr_device("mirny0_ch0")
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self.setattr_device("mirny0_ch0")
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