forked from M-Labs/artiq
gateware: rewrite mailbox to use bits_for.
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43cd970100
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@ -12,10 +12,10 @@ class Mailbox(Module):
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values = Array([Signal(32) for _ in range(size)])
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for i in self.i1, self.i2:
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self.sync += [
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i.dat_r.eq(values[i.adr & 0xff]),
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i.dat_r.eq(values[i.adr[:bits_for(size-1)]]),
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i.ack.eq(0),
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If(i.cyc & i.stb & ~i.ack,
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i.ack.eq(1),
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If(i.we, values[i.adr & 0xff].eq(i.dat_w))
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If(i.we, values[i.adr[:bits_for(size-1)]].eq(i.dat_w))
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)
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]
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