forked from M-Labs/artiq
gateware: rewrite mailbox to use bits_for.
This commit is contained in:
parent
43cd970100
commit
636d4efe81
@ -12,10 +12,10 @@ class Mailbox(Module):
|
||||
values = Array([Signal(32) for _ in range(size)])
|
||||
for i in self.i1, self.i2:
|
||||
self.sync += [
|
||||
i.dat_r.eq(values[i.adr & 0xff]),
|
||||
i.dat_r.eq(values[i.adr[:bits_for(size-1)]]),
|
||||
i.ack.eq(0),
|
||||
If(i.cyc & i.stb & ~i.ack,
|
||||
i.ack.eq(1),
|
||||
If(i.we, values[i.adr & 0xff].eq(i.dat_w))
|
||||
If(i.we, values[i.adr[:bits_for(size-1)]].eq(i.dat_w))
|
||||
)
|
||||
]
|
||||
|
Loading…
Reference in New Issue
Block a user